From 9c6cdff7853e74592a5da0e4a4e2e80f705a0ba5 Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Fri, 31 Jan 2020 11:10:09 +0100 Subject: [PATCH] A CPU with 5-level paging is available now --- .../second-edition/posts/08-paging-introduction/index.md | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/blog/content/second-edition/posts/08-paging-introduction/index.md b/blog/content/second-edition/posts/08-paging-introduction/index.md index 29f8784c..71c75ace 100644 --- a/blog/content/second-edition/posts/08-paging-introduction/index.md +++ b/blog/content/second-edition/posts/08-paging-introduction/index.md @@ -141,7 +141,7 @@ The page table index for level is derived directly from the virtual address: ![Bits 0–12 are the page offset, bits 12–21 the level 1 index, bits 21–30 the level 2 index, bits 30–39 the level 3 index, and bits 39–48 the level 4 index](x86_64-table-indices-from-address.svg) -We see that each table index consists of 9 bits, which makes sense because each table has 2^9 = 512 entries. The lowest 12 bits are the offset in the 4KiB page (2^12 bytes = 4KiB). Bits 48 to 64 are discarded, which means that x86_64 is not really 64-bit since it only supports 48-bit addresses. There are plans to extend the address size to 57 bits through a [5-level page table], but no processor that supports this feature exists yet. +We see that each table index consists of 9 bits, which makes sense because each table has 2^9 = 512 entries. The lowest 12 bits are the offset in the 4KiB page (2^12 bytes = 4KiB). Bits 48 to 64 are discarded, which means that x86_64 is not really 64-bit since it only supports 48-bit addresses. [5-level page table]: https://en.wikipedia.org/wiki/Intel_5-level_paging @@ -149,6 +149,10 @@ Even though bits 48 to 64 are discarded, they can't be set to arbitrary values. [sign extension in two's complement]: https://en.wikipedia.org/wiki/Two's_complement#Sign_extension +It's worth noting that the recent "Ice Lake" Intel CPUs optionally support [5-level page tables] to extends virtual addresses from 48-bit to 57-bit. Given that optimizing our kernel for a specific CPU does not make sense at this stage, we will only work with standard 4-level page tables in this post. + +[5-level page tables]: https://en.wikipedia.org/wiki/Intel_5-level_paging + ### Example Translation Let's go through an example to understand how the translation process works in detail: