From 812c981f9b28f99407530a64d72a0180b8fbc3e1 Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Mon, 13 Aug 2018 17:07:13 +0200 Subject: [PATCH] Self-host math picture --- .../03-returning-from-exceptions/index.md | 2 +- .../vector-addition.png | Bin 0 -> 2236 bytes 2 files changed, 1 insertion(+), 1 deletion(-) create mode 100644 blog/content/first-edition/extra/naked-exceptions/03-returning-from-exceptions/vector-addition.png diff --git a/blog/content/first-edition/extra/naked-exceptions/03-returning-from-exceptions/index.md b/blog/content/first-edition/extra/naked-exceptions/03-returning-from-exceptions/index.md index be5421a1..d88f8f78 100644 --- a/blog/content/first-edition/extra/naked-exceptions/03-returning-from-exceptions/index.md +++ b/blog/content/first-edition/extra/naked-exceptions/03-returning-from-exceptions/index.md @@ -429,7 +429,7 @@ When we discussed calling conventions above, we assummed that a x86_64 CPU only However, modern CPUs also have a set of _special purpose registers_, which can be used to improve performance in several use cases. On x86_64, the most important set of special purpose registers are the _multimedia registers_. These registers are larger than the general purpose registers and can be used to speed up audio/video processing or matrix calculations. For example, we could use them to add two 4-dimensional vectors _in a single CPU instruction_: -![`(1,2,3,4) + (5,6,7,8) = (6,8,10,12)`](http://mathurl.com/jz3nvev.png) +![`(1,2,3,4) + (5,6,7,8) = (6,8,10,12)`](vector-addition.png) Such multimedia instructions are called [Single Instruction Multiple Data (SIMD)] instructions, because they simultaneously perform an operation (e.g. addition) on multiple data words. Good compilers are able to transform normal loops into such SIMD code automatically. This process is called [auto-vectorization] and can lead to huge performance improvements. diff --git a/blog/content/first-edition/extra/naked-exceptions/03-returning-from-exceptions/vector-addition.png b/blog/content/first-edition/extra/naked-exceptions/03-returning-from-exceptions/vector-addition.png new file mode 100644 index 0000000000000000000000000000000000000000..2036edfb1545637945e63f6c431eabcff2b4753e GIT binary patch literal 2236 zcmeAS@N?(olHy`uVBq!ia0y~yV3@_gz!1Q}%)r2KEojbn1_lP#0G|-o|Ns9pPz>Y} zm%n6SU=S+_@(X4tn;EkEu9A_!*|biV)$b2pzo_tXqd{!-@>&K42F?PH$YKTtz9S&a zI8~cZnt_4+x2KC^NCxZMsM}(z)dXC9udLWO{qnE>^KZ>;+}X%dbnaE~YiE~)_cx1V zkF^}QexP%M&!jhA9G{{SIG9A8&1Du}{5)%EntRiP*L$3GEqhiT z`t+zuw%kSTdg)yD2m2Y@1bQd+CQ59}So5I5$yxSs#j!_)?=MVQrBF1huT^e8V_U<8 z3fsO7F*n{7q{=+@*cm)&TO8A(Km7JBa~5q7*vHV+mLYP&{KeX-vkw<szMA$wn!k{j~d+TK~c+uDoTht|`dyXGST%HAuc_@GHe>-3|xcOpX%9M4^tr z1vLrVGuxf`mv=Ta8^pOqU5L@seILWlnKJd!nN7RS7H;L6;WYW`EHCwGyWgCDt-JPD zRn)TETNDl(^xS7~BPn>Dluzox3uLj6S9o%Ye67l4GsB+iHG%wj3z+0!?Z@wB@u+-| z*Lt+0qBp|-1^eShUtR8|Gc~`}1eR>PctcYE z%e}4pA23>8JDsX~E33VjPpSQHXv(wO+Z%2$oYUZ_JiA+t;{aDt%2v19xsN9uo)M~& z>6*5$mOH|WIXBW;;rN?vQ=eX8esSr}^NI%`@s8&lZO6o8+e^P(n~=P(ZgN?}SGTDL z?Y>Xf)STRPrslVpz|zRY31T<)9&VC({dISgY@yKS#o7;jip`&zI2_$>&bn-uZ<=Y+ zid2Dg=~YR*vW6S>9Po%q-MK||+VsoI?)?6?tl@Rq_ch0S>M`!(A$+Tj9wYFXD+J=e^?-muV>D*#IMWTM~h7XRnN@R|o zU_8(CBT%Y-twU`4j1x;88#%?q#8||AXBOFTd)(PC!zsVC(b|Q*RXy+Ca#@jM3`QO+ zjLyZoud4OEDH+6{9ohJ}gMS~JXY@-4J$Zo*ZR=f^uR8M7+lzT$&Bfp;`WlTtqbF}s z_IiA=O{OosLUR7esdpqkJmr7ab>{=`CFx#StBI$b-L+jrE*%iv=Do^if_2q-``NqV zKFeOaz94M&imP+B*sqrtt9g<5K0iJwJMflbdF|2*Ol=PqY`nUO&y}yZ$$`E6nsfN; zFNqT_+_Ld-DCM3ZAHCx0qw2nTJkH{d=z@ zW5H49r05fgSr2z@{XD5p%Rbt`qeJA+CX+uV9qBz46AO9m8`}5Hp5b9^x47By<>i zN(%q;EoeMtKl4s__mPhV$youJYA1PT-e>g`s_cKw(6l_M$Bq3??N$$&wk+d%(^oUn zn?PC=);+&udolhq$T%hM*F`L@9{Epmm!5}6?lP6~SQ4fj_A~3CjQadX2Q~_3imguC zG)2Mp&VFu==HA{nis;DH9Ju}9iQ=WUYgN7>nMZEys29I5S8M6jC#zcvbPC;P zZR~Wt)toNxwIY`D<)eSG4sQZG)4NT6W-XNQFG}AosP~Vb>%a2~HLa)aOL~8oGaXD7 zm!GxtWH|TXjVFDk*-z!2^ffTX<<^dRb%AeM8z(Gz8P0vWalZ6Rq0CP&pDZ?#INM@U z_&-j;xzXOsI9^xh_`GeW-xePI{9C1PV%wIED?94V1@`o3OgYac!mgZty!b{id)G$B zw)2mSQtSn0t$kEm!S|hCH{;Q?%L|KYL;o+?nio9vRHa!hgK$%@+P0KXVZNWd0%n(@ z&ucu7m@oB`bGL