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Introduction to Paging: fix typo (sized -> size)
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@@ -135,7 +135,7 @@ Now that we know how paging and multilevel page tables works, we can look at how
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## Paging on x86_64
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## Paging on x86_64
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The x86_64 architecture uses a 4-level page table and a page size of 4KiB. Each page table, independent of the level, has a fixed sized of 512 entries. Each entry has a size of 8 bytes, so each table is 512 * 8B = 4KiB large and thus fits exactly into one page.
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The x86_64 architecture uses a 4-level page table and a page size of 4KiB. Each page table, independent of the level, has a fixed size of 512 entries. Each entry has a size of 8 bytes, so each table is 512 * 8B = 4KiB large and thus fits exactly into one page.
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The page table index for level is derived directly from the virtual address:
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The page table index for level is derived directly from the virtual address:
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