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Update posts to use x86_64 crate

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This commit is contained in:
Philipp Oppermann
2017-03-15 16:57:02 +01:00
parent 02eaeb7af1
commit 4853baaabc
6 changed files with 46 additions and 50 deletions
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17
blog/content/post/06-page-tables.md
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@@ -898,18 +898,15 @@ An x86 processor has many different caches because always accessing the main mem
The translation lookaside buffer, or TLB, caches the translation of virtual to physical addresses. It's filled automatically when a page is accessed. But it's not updated transparently when the mapping of a page changes. This is the reason that we still can access the page even through we unmapped it in the page table.
So to fix our `unmap` function, we need to remove the cached translation from the TLB. We can use Gerd Zellweger's [x86][x86 crate] crate to do this easily. To add it, we append the following to our `Cargo.toml`:
So to fix our `unmap` function, we need to remove the cached translation from the TLB. We can use the [x86_64][x86_64 crate] crate to do this easily. To add it, we append the following to our `Cargo.toml`:
[x86 crate]: https://github.com/gz/rust-x86
[x86_64 crate]: https://docs.rs/x86_64
```toml
[dependencies.x86]
version = "0.8.0"
default-features = false
[dependencies]
...
x86_64 = "0.1.0"
```
It has a `performance-counter` feature that allows reading the CPU specific [performance counters] but increases compile times. We don't need it right now, so we disable it using `default-features = false`.
[performance counters]: http://gz.github.io/rust-x86/x86/perfcnt/index.html
Now we can use it to fix `unmap`:
@@ -917,7 +914,9 @@ It has a `performance-counter` feature that allows reading the CPU specific [per
...
p1[page.p1_index()].set_unused();
unsafe {
::x86::shared::tlb::flush(page.start_address());
use x86_64::instructions::tlb;
use x86_64::VirtualAddress;
tlb::flush(VirtualAddress(page.start_address()));
}
// TODO free p(1,2,3) table if empty
//allocator.deallocate_frame(frame);

21
blog/content/post/07-remap-the-kernel.md
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@@ -345,12 +345,11 @@ pub fn with<F>(&mut self,
f: F)
where F: FnOnce(&mut ActivePageTable)
{
use x86::shared::tlb;
let flush_tlb = || unsafe { tlb::flush_all() };
use x86_64::instructions::tlb;
// overwrite recursive mapping
self.p4_mut()[511].set(table.p4_frame.clone(), PRESENT | WRITABLE);
flush_tlb();
tlb::flush_all();
// execute f in the new context
f(self);
@@ -449,7 +448,7 @@ Right now, the `with` function overwrites the recursive mapping and calls the cl
To backup the physical P4 frame of the active table, we can either read it from the 511th P4 entry (before we change it) or from the CR3 control register directly. We will do the latter as it should be faster and we already have a external crate that makes it easy:
```rust
use x86::shared::control_regs;
use x86_64::shared::control_regs;
let backup = Frame::containing_address(
unsafe { control_regs::cr3() } as usize
);
@@ -482,8 +481,8 @@ pub fn with<F>(&mut self,
f: F)
where F: FnOnce(&mut Mapper)
{
use x86::shared::{control_regs, tlb};
let flush_tlb = || unsafe { tlb::flush_all() };
use x86_64::instructions::tlb;
use x86_64::shared::{control_regs, tlb};
{
let backup = Frame::containing_address(
@@ -494,14 +493,14 @@ pub fn with<F>(&mut self,
// overwrite recursive mapping
self.p4_mut()[511].set(table.p4_frame.clone(), PRESENT | WRITABLE);
flush_tlb();
tlb::flush_all();
// execute f in the new context
f(self);
// restore recursive mapping to original p4 table
p4_table[511].set(backup, PRESENT | WRITABLE);
flush_tlb();
tlb::flush_all();
}
temporary_page.unmap(self);
@@ -755,7 +754,7 @@ We do this in a new `ActivePageTable::switch` method:
// in `impl ActivePageTable` in src/memory/paging/mod.rs
pub fn switch(&mut self, new_table: InactivePageTable) -> InactivePageTable {
use x86::shared::control_regs;
use x86_64::shared::control_regs;
let old_table = InactivePageTable {
p4_frame: Frame::containing_address(
@@ -976,7 +975,7 @@ So we need to enable the `NXE` bit. For that we use the awesome [x86][rust-x86]
// in lib.rs
fn enable_nxe_bit() {
use x86::shared::msr::{IA32_EFER, rdmsr, wrmsr};
use x86_64::shared::msr::{IA32_EFER, rdmsr, wrmsr};
let nxe_bit = 1 << 11;
unsafe {
@@ -996,7 +995,7 @@ Right now, we are still able to modify the `.code` and `.rodata` sections, even
// in lib.rs
fn enable_write_protect_bit() {
use x86::shared::control_regs::{cr0, cr0_write, CR0_WRITE_PROTECT};
use x86_64::shared::control_regs::{cr0, cr0_write, CR0_WRITE_PROTECT};
unsafe { cr0_write(cr0() | CR0_WRITE_PROTECT) };
}

24
blog/content/post/09-catching-exceptions.md
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@@ -84,8 +84,9 @@ Now we create types for the IDT and its entries:
```rust
// src/interrupts/idt.rs
use x86::shared::segmentation::{self, SegmentSelector};
use x86::shared::PrivilegeLevel;
use x86_64::instructions::segmentation;
use x86_64::structures::gdt::SegmentSelector;
use x86_64::PrivilegeLevel;
pub struct Idt([Entry; 16]);
@@ -279,10 +280,9 @@ impl Idt {
}
}
```
The method overwrites the specified entry with the given handler function. We use the `segmentation::cs`[^fn-segmentation-cs] function of the [x86 crate] to get the current code segment descriptor. There's no need for different kernel code segments in long mode, so the current `cs` value should be always the right choice.
The method overwrites the specified entry with the given handler function. We use the `segmentation::cs` function of the [x86_64 crate] to get the current code segment descriptor. There's no need for different kernel code segments in long mode, so the current `cs` value should be always the right choice.
[x86 crate]: https://github.com/gz/rust-x86
[^fn-segmentation-cs]: The `segmentation::cs` function was [added](https://github.com/gz/rust-x86/pull/12) in version 0.7.0, so you might need to update your `x86` version in your `Cargo.toml`.
[x86_64 crate]: https://docs.rs/x86_64
By returning a mutual reference to the entry's options, we allow the caller to override the default settings. For example, the caller could add a non-present entry by executing: `idt.set_handler(11, handler_fn).set_present(false)`.
@@ -299,19 +299,19 @@ Type | Name | Description
u16 | Limit | The maximum addressable byte in the table. Equal to the table size in bytes minus 1.
u64 | Offset | Virtual start address of the table.
This structure is already contained [in the x86 crate], so we don't need to create it ourselves. The same is true for the [lidt function]. So we just need to put the pieces together to create a `load` method:
This structure is already contained [in the x86_64 crate], so we don't need to create it ourselves. The same is true for the [lidt function]. So we just need to put the pieces together to create a `load` method:
[in the x86 crate]: http://gz.github.io/rust-x86/x86/dtables/struct.DescriptorTablePointer.html
[lidt function]: http://gz.github.io/rust-x86/x86/dtables/fn.lidt.html
[in the x86_64 crate]: http://docs.rs/x86_64/0.1.0/x86_64/instructions/tables/struct.DescriptorTablePointer.html
[lidt function]: http://docs.rs/x86_64/0.1.0/x86_64/instructions/tables/fn.lidt.html
```rust
impl Idt {
pub fn load(&self) {
use x86::shared::dtables::{DescriptorTablePointer, lidt};
use x86_64::instructions::tables::{DescriptorTablePointer, lidt};
use core::mem::size_of;
let ptr = DescriptorTablePointer {
base: self as *const _ as *const ::x86::bits64::irq::IdtEntry,
base: self as *const _ as u64,
limit: (size_of::<Self>() - 1) as u16,
};
@@ -319,9 +319,7 @@ impl Idt {
}
}
```
The method does not need to modify the IDT, so it takes `self` by immutable reference. First, we create a `DescriptorTablePointer` and then we pass it to `lidt`. The `lidt` function expects that the `base` field has the type `x86::bits64::irq::IdtEntry`[^fn-x86-idt-entry], therefore we need to cast the `self` pointer. For calculating the `limit` we use [mem::size_of]. The additional `-1` is needed because the limit field has to be the maximum addressable byte (inclusive bound). We need an unsafe block around `lidt`, because the function assumes that the specified handler addresses are valid.
[^fn-x86-idt-entry]: The `x86` crate has its own `IdtEntry` type, but it is a bit incomplete. Therefore we created our own IDT types.
The method does not need to modify the IDT, so it takes `self` by immutable reference. First, we create a `DescriptorTablePointer` and then we pass it to `lidt`. The `lidt` function expects that the `base` field has the type `u64`, therefore we need to cast the `self` pointer. For calculating the `limit` we use [mem::size_of]. The additional `-1` is needed because the limit field has to be the maximum addressable byte (inclusive bound). We need an unsafe block around `lidt`, because the function assumes that the specified handler addresses are valid.
[mem::size_of]: https://doc.rust-lang.org/nightly/core/mem/fn.size_of.html

4
blog/content/post/10-better-exception-messages.md
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@@ -148,7 +148,7 @@ If you want to try it, insert it in `src/lib.rs` and call it from `rust_main`. W
[...]
000000000010df90 <_ZN7blog_os22naked_function_example17ha9f733dfe42b595dE>:
10df90: 48 c7 c0 2a 00 00 00 mov $0x42,%rax
10df97: c3 retq
10df97: c3 retq
10df98: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1)
10df9f: 00
```
@@ -629,7 +629,7 @@ Now we can improve our page fault error message by using the new `PageFaultError
extern "C" fn page_fault_handler(stack_frame: &ExceptionStackFrame,
error_code: u64) -> !
{
use x86::shared::control_regs;
use x86_64::registers::control_regs;
println!(
"\nEXCEPTION: PAGE FAULT while accessing {:#x}\
\nerror code: {:?}\n{:#?}",

2
blog/content/post/11-returning-from-exceptions.md
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@@ -79,7 +79,7 @@ In order to test it, we insert an `int3` instruction in our `rust_main`:
// in src/lib.rs
...
#[macro_use] // needed for the `int!` macro
extern crate x86;
extern crate x86_64;
...
#[no_mangle]

28
blog/content/post/12-double-faults.md
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@@ -41,10 +41,9 @@ pub extern "C" fn rust_main(multiboot_information_address: usize) {
}
{{< / highlight >}}
We use the [int! macro] of the [x86 crate] to trigger the exception with vector number `1`, which is the [debug exception]. The debug exception occurs for example when a breakpoint defined in the [debug registers] is hit. Like the [breakpoint exception], it is mainly used for [implementing debuggers].
We use the [int! macro] of the `x86_64` crate to trigger the exception with vector number `1`, which is the [debug exception]. The debug exception occurs for example when a breakpoint defined in the [debug registers] is hit. Like the [breakpoint exception], it is mainly used for [implementing debuggers].
[int! macro]: https://docs.rs/x86/0.8.0/x86/macro.int!.html
[x86 crate]: https://github.com/gz/rust-x86
[int! macro]: https://docs.rs/x86_64/0.1.0/x86_64/macro.int!.html
[debug exception]: http://wiki.osdev.org/Exceptions#Debug
[debug registers]: https://en.wikipedia.org/wiki/X86_debug_register
[breakpoint exception]: http://wiki.osdev.org/Exceptions#Breakpoint
@@ -476,7 +475,7 @@ Let's create a new TSS that contains our double fault stack in its interrupt sta
```rust
// in src/interrupts/mod.rs
use x86::bits64::task::TaskStateSegment;
use x86_64::structures::tss::TaskStateSegment;
```
Let's create a new TSS in our `interrupts::init` function:
@@ -624,7 +623,7 @@ Let's add a function to our descriptor that creates a TSS descriptor for a given
```rust
// in src/interrupts/gdt.rs
use x86::bits64::task::TaskStateSegment;
use x86_64::structures::tss::TaskStateSegment;
impl Descriptor {
pub fn tss_segment(tss: &'static TaskStateSegment) -> Descriptor {
@@ -660,8 +659,8 @@ In order to add descriptors to the GDT, we add a `add_entry` method:
```rust
// in src/interrupts/gdt.rs
use x86::shared::segmentation::SegmentSelector;
use x86::shared::PrivilegeLevel;
use x86_64::structures::gdt::SegmentSelector;
use x86_64::PrivilegeLevel;
impl Gdt {
pub fn add_entry(&mut self, entry: Descriptor) -> SegmentSelector {
@@ -709,8 +708,8 @@ To load the GDT, we add a new `load` method:
impl Gdt {
pub fn load(&'static self) {
use x86::shared::dtables::{DescriptorTablePointer, lgdt};
use x86::shared::segmentation;
use x86_64::instructions::tables::{DescriptorTablePointer, lgdt};
use x86_64::instructions::segmentation;
use core::mem::size_of;
let ptr = DescriptorTablePointer {
@@ -847,8 +846,9 @@ For the first two steps, we need access to the `code_selector` and `tss_selector
{{< highlight rust "hl_lines=3 4 7 8 11 12 19 21" >}}
// in src/interrupts/mod.rs
pub fn init(memory_controller: &mut MemoryController) {
use x86::shared::segmentation::{SegmentSelector, set_cs};
use x86::shared::task::load_tr;
use x86_64::structures::gdt::SegmentSelector;
use x86_64::instructions::segmentation::set_cs;
use x86_64::instructions::tables::load_tss;
...
let mut code_selector = SegmentSelector::empty();
@@ -865,17 +865,17 @@ pub fn init(memory_controller: &mut MemoryController) {
// reload code segment register
set_cs(code_selector);
// load TSS
load_tr(tss_selector);
load_tss(tss_selector);
}
IDT.load();
}
{{< / highlight >}}
We first set the descriptors to `empty` and then update them from inside the closure (which implicitly borrows them as `&mut`). Now we're able to reload the code segment register using [`set_cs`] and to load the TSS using [`load_tr`].
We first set the descriptors to `empty` and then update them from inside the closure (which implicitly borrows them as `&mut`). Now we're able to reload the code segment register using [`set_cs`] and to load the TSS using [`load_tss`].
[`set_cs`]: https://docs.rs/x86/0.8.0/x86/shared/segmentation/fn.set_cs.html
[`load_tr`]: https://docs.rs/x86/0.8.0/x86/shared/task/fn.load_tr.html
[`load_tss`]: https://docs.rs/x86/0.8.0/x86/shared/task/fn.load_tss.html
Now that we loaded a valid TSS and interrupt stack table, we can set the stack index for our double fault handler in the IDT: