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Merge pull request #281 from phil-opp/update-bit_field

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Update to latest bit_field version
This commit is contained in:
Philipp Oppermann
2017-01-25 13:49:49 +01:00
committed by GitHub
parent fce85e68ee 8b807a7d25
commit 419d000897
5 changed files with 19 additions and 19 deletions
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2
Cargo.toml
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@@ -4,7 +4,7 @@ name = "blog_os"
version = "0.1.0" version = "0.1.0"
[dependencies] [dependencies]
bit_field = "0.5.0" bit_field = "0.7.0"
bitflags = "0.7.0" bitflags = "0.7.0"
multiboot2 = "0.1.0" multiboot2 = "0.1.0"
once = "0.3.2" once = "0.3.2"

8
blog/post/09-catching-exceptions.md
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@@ -148,7 +148,7 @@ Well, none of these variants is really _readable_ and it's very easy to make mis
[Range]: https://doc.rust-lang.org/nightly/core/ops/struct.Range.html [Range]: https://doc.rust-lang.org/nightly/core/ops/struct.Range.html
``` rust ``` rust
self.0.set_range(0..3, stack_index); self.0.set_bits(0..3, stack_index);
``` ```
I think it is much more readable, since we abstracted away all bit-masking details. The `BitField` trait is contained in the [bit_field] crate. (It's pretty new, so it might still contain bugs.) To add it as dependency, we run `cargo add bit_field` and add `extern crate bit_field;` to our `src/lib.rs`. I think it is much more readable, since we abstracted away all bit-masking details. The `BitField` trait is contained in the [bit_field] crate. (It's pretty new, so it might still contain bugs.) To add it as dependency, we run `cargo add bit_field` and add `extern crate bit_field;` to our `src/lib.rs`.
@@ -168,7 +168,7 @@ pub struct EntryOptions(u16);
impl EntryOptions { impl EntryOptions {
fn minimal() -> Self { fn minimal() -> Self {
let mut options = 0; let mut options = 0;
options.set_range(9..12, 0b111); // 'must-be-one' bits options.set_bits(9..12, 0b111); // 'must-be-one' bits
EntryOptions(options) EntryOptions(options)
} }
@@ -189,12 +189,12 @@ impl EntryOptions {
} }
pub fn set_privilege_level(&mut self, dpl: u16) -> &mut Self { pub fn set_privilege_level(&mut self, dpl: u16) -> &mut Self {
self.0.set_range(13..15, dpl); self.0.set_bits(13..15, dpl);
self self
} }
pub fn set_stack_index(&mut self, index: u16) -> &mut Self { pub fn set_stack_index(&mut self, index: u16) -> &mut Self {
self.0.set_range(0..3, index); self.0.set_bits(0..3, index);
self self
} }
} }

12
blog/post/12-double-faults.md
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@@ -635,15 +635,15 @@ impl Descriptor {
let mut low = PRESENT.bits(); let mut low = PRESENT.bits();
// base // base
low.set_range(16..40, ptr.get_range(0..24)); low.set_bits(16..40, ptr.get_bits(0..24));
low.set_range(56..64, ptr.get_range(24..32)); low.set_bits(56..64, ptr.get_bits(24..32));
// limit (the `-1` in needed since the bound is inclusive) // limit (the `-1` in needed since the bound is inclusive)
low.set_range(0..16, (size_of::<TaskStateSegment>() - 1) as u64); low.set_bits(0..16, (size_of::<TaskStateSegment>() - 1) as u64);
// type (0b1001 = available 64-bit tss) // type (0b1001 = available 64-bit tss)
low.set_range(40..44, 0b1001); low.set_bits(40..44, 0b1001);
let mut high = 0; let mut high = 0;
high.set_range(0..32, ptr.get_range(32..64)); high.set_bits(0..32, ptr.get_bits(32..64));
Descriptor::SystemSegment(low, high) Descriptor::SystemSegment(low, high)
} }
@@ -900,7 +900,7 @@ We also rewrite the `set_stack_index` method in `src/interrupts/idt.rs`:
pub fn set_stack_index(&mut self, index: u16) -> &mut Self { pub fn set_stack_index(&mut self, index: u16) -> &mut Self {
// The hardware IST index starts at 1, but our software IST index // The hardware IST index starts at 1, but our software IST index
// starts at 0. Therefore we need to add 1 here. // starts at 0. Therefore we need to add 1 here.
self.0.set_range(0..3, index + 1); self.0.set_bits(0..3, index + 1);
self self
} }
``` ```

10
src/interrupts/gdt.rs
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@@ -71,15 +71,15 @@ impl Descriptor {
let mut low = PRESENT.bits(); let mut low = PRESENT.bits();
// base // base
low.set_range(16..40, ptr.get_range(0..24)); low.set_bits(16..40, ptr.get_bits(0..24));
low.set_range(56..64, ptr.get_range(24..32)); low.set_bits(56..64, ptr.get_bits(24..32));
// limit (the `-1` in needed since the bound is inclusive) // limit (the `-1` in needed since the bound is inclusive)
low.set_range(0..16, (size_of::<TaskStateSegment>() - 1) as u64); low.set_bits(0..16, (size_of::<TaskStateSegment>() - 1) as u64);
// type (0b1001 = available 64-bit tss) // type (0b1001 = available 64-bit tss)
low.set_range(40..44, 0b1001); low.set_bits(40..44, 0b1001);
let mut high = 0; let mut high = 0;
high.set_range(0..32, ptr.get_range(32..64)); high.set_bits(0..32, ptr.get_bits(32..64));
Descriptor::SystemSegment(low, high) Descriptor::SystemSegment(low, high)
} }

6
src/interrupts/idt.rs
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@@ -81,7 +81,7 @@ pub struct EntryOptions(u16);
impl EntryOptions { impl EntryOptions {
fn minimal() -> Self { fn minimal() -> Self {
let mut options = 0; let mut options = 0;
options.set_range(9..12, 0b111); // 'must-be-one' bits options.set_bits(9..12, 0b111); // 'must-be-one' bits
EntryOptions(options) EntryOptions(options)
} }
@@ -103,14 +103,14 @@ impl EntryOptions {
#[allow(dead_code)] #[allow(dead_code)]
pub fn set_privilege_level(&mut self, dpl: u16) -> &mut Self { pub fn set_privilege_level(&mut self, dpl: u16) -> &mut Self {
self.0.set_range(13..15, dpl); self.0.set_bits(13..15, dpl);
self self
} }
pub fn set_stack_index(&mut self, index: u16) -> &mut Self { pub fn set_stack_index(&mut self, index: u16) -> &mut Self {
// The hardware IST index starts at 1, but our software IST index // The hardware IST index starts at 1, but our software IST index
// starts at 0. Therefore we need to add 1 here. // starts at 0. Therefore we need to add 1 here.
self.0.set_range(0..3, index + 1); self.0.set_bits(0..3, index + 1);
self self
} }
} }