Update blog to 52f239e5b4

_posts/2015-12-09-modifying-page-tables.md

@@ -864,12 +864,16 @@ An x86 processor has many different caches because always accessing the main mem
 
 The translation lookaside buffer, or TLB, caches the translation of virtual to physical addresses. It's filled automatically when a page is accessed. But it's not updated transparently when the mapping of a page changes. This is the reason that we still can access the page even through we unmapped it in the page table.
 
-So to fix our `unmap` function, we need to remove the cached translation from the TLB. We can use Gerd Zellweger's x86 crate to do this easily. To add it, append `x86 = "0.5.0"` to the dependency section in the `Cargo.toml`. Then we can use it to fix `unmap`:
+So to fix our `unmap` function, we need to remove the cached translation from the TLB. We can use Gerd Zellweger's [x86][x86 crate] crate to do this easily. To add it, append `x86 = "0.5.0"` to the dependency section in the `Cargo.toml`. Then we can use it to fix `unmap`:
+
+[x86 crate]: https://github.com/gz/rust-x86
 
 ```rust
 ...
   p1[page.p1_index()].set_unused();
-  unsafe { ::x86::tlb::flush(page.start_address() )};
+  unsafe {
+      ::x86::tlb::flush(page.start_address());
+  }
   // TODO free p(1,2,3) table if empty
   //allocator.deallocate_frame(frame);
 }