From 2ad8de51de5e2e343e26a31b1132c8ef28efe704 Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Fri, 21 Dec 2018 00:49:22 +0100 Subject: [PATCH 01/29] Begin second paging post --- .../identity-mapped-page-tables.svg | 2 + .../second-edition/posts/10-paging-2/index.md | 134 ++++++++++++++++++ .../10-paging-2/recursive-page-table.svg | 2 + .../temporarily-mapped-page-tables.svg | 2 + 4 files changed, 140 insertions(+) create mode 100644 blog/content/second-edition/posts/10-paging-2/identity-mapped-page-tables.svg create mode 100644 blog/content/second-edition/posts/10-paging-2/index.md create mode 100644 blog/content/second-edition/posts/10-paging-2/recursive-page-table.svg create mode 100644 blog/content/second-edition/posts/10-paging-2/temporarily-mapped-page-tables.svg diff --git a/blog/content/second-edition/posts/10-paging-2/identity-mapped-page-tables.svg b/blog/content/second-edition/posts/10-paging-2/identity-mapped-page-tables.svg new file mode 100644 index 00000000..ad9b0aa9 --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/identity-mapped-page-tables.svg @@ -0,0 +1,2 @@ + +
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<div>1000KiB</div> \ No newline at end of file diff --git a/blog/content/second-edition/posts/10-paging-2/index.md b/blog/content/second-edition/posts/10-paging-2/index.md new file mode 100644 index 00000000..62295d35 --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/index.md @@ -0,0 +1,134 @@ ++++ +title = "Paging 2" +order = 10 +path = "paging-2" +date = 0000-01-01 +template = "second-edition/page.html" ++++ + +This post TODO + + + +This blog is openly developed on [Github]. If you have any problems or questions, please open an issue there. You can also leave comments [at the bottom]. + +[Github]: https://github.com/phil-opp/blog_os +[at the bottom]: #comments + +## Introduction + +In the [previous post] we learned about the principles of paging and how the 4-level page tables on the x86_64 architecture work. One thing that the post did not mention: **Our kernel already runs on paging**. The bootloader that we added in the ["A minimal Rust Kernel"] post already set up a 4-level paging hierarchy that maps every page of our kernel to a physical frame. The reason why the bootloader does this is that paging is manditory in 64-bit mode on x86_64. + +[previous post]: ./second-edition/posts/09-paging/index.md +["A minimal Rust kernel"]: ./second-edition/posts/02-minimal-rust-kernel/index.md#creating-a-bootimage + +The bootloader also sets the correct access permissions for each page, which means that only the pages containing code are executable and only data pages are writable. You can try this by accessing some memory outside our kernel: + +```rust +let ptr = 0xdeadbeaf as *mut u32; +unsafe { *ptr = 42; } +``` + +You will see that this results in an page fault exception. (We don't have page fault handler, so you will see that the double fault handler is invoked.) + +In case you are wondering how we could access the physical address `0xb8000` in order to print to the [VGA text buffer]: The bootloader identity mapped this frame, which means that it set up a page at the virtual address `0xb8000` that points to the physical frame with the same address. + +[VGA text buffer]: ./second-edition/posts/03-vga-text-buffer/index.md + +The question is: How do we access the page tables that our kernel runs to create new page mappings? + +## Accessing Page Tables + +Accessing the page tables from our kernel is not as easy as it may seem. To understand the problem let's take a look at the example 4-level page table hierarchy of the previous post again: + +![An example 4-level page hierarchy with each page table shown in physical memory](../paging/x86_64-page-table-translation.svg) + +The important thing here is that each page entry stores the _physical_ address of the next table. This avoids the need to run a translation for these addresses too, which would be bad for performance and could easily cause endless translation loops. + +The problem for us is that we can't directly access physical addresses from our kernel, since our kernel also runs on top of virtual addresses. For example when we access address 4KiB, we access the _virtual_ address 4KiB, not the _physical_ address 4KiB where the level 4 page table lives. When we want to acccess the physical address 4KiB, we can only do so through some virtual address that maps to it. + +So in order access page table frames, we need to map some virtual pages to them. There are different ways to create these mappings that all allow us to access arbitrary page table frames: + + +- A simple solution is to **identity map all page tables** like the VGA text buffer: + + ![A virtual and a physical address space with various virtual pages mapped to the physical frame with the same address](identity-mapped-page-tables.svg) + + In this example we see various identity-mapped page table frames. This way the physical addresses in the page tables are also valid virtual addresses so that we can easily access the page tables of all levels starting from the CR3 register. + + However, it clutters the virtual address space and makes it more difficult to find continuous memory regions of larger sizes. For example, imagine that we want to create a virtual memory region of size 1000 KiB in the above graphic, e.g. for [memory-mapping a file]. We can't start the region at 26 KiB because it would collide with the already mapped page at 1004 MiB. So we have to look further until we find a large enough unmapped area, for example at 1008 KiB. This is a similar fragmentation problem as with [segmentation]. + + [memory-mapping a file]: https://en.wikipedia.org/wiki/Memory-mapped_file + [segmentation]: ./second-edition/posts/09-paging/index.md#fragmentation + + Equally, it makes it much more difficult to create new page tables, because we need to find physical frames whose corresponding pages aren't already in use. For example, let's assume that we reserved the 1000 KiB memory region starting at 1008 KiB for our memory-mapped file. Now we can't use any frame with a _physical_ address between 1000 KiB and 2008 KiB anymore, because we can't identity map it. + +- Alternatively, we could **map the page tables frames only temporarily** when we need to access them. To be able to create the temporary mappings, we could identity map some level 1 table: + + ![A virtual and a physical address space with an identity mapped level 1 table, which maps its 0th entry to the level 2 table frame, therey mapping that frame to page with address 0](temporarily-mapped-page-tables.svg) + + The level 1 table in this graphic controls the first 2 MiB of the virtual address space. This is because it is reachable by starting at the CR3 register and following the 0th entry in the level 4, level 3, and level 2 page tables. The entry with index 8 maps the virtual page at address 32 KiB to the physical frame at address 32 KiB, thereby identity mapping the level 1 table it is contained in. The graphic shows this identity-mapping by the horizontal arrow at 32 KiB. + + By writing the identity-mapped level 1 table our kernel can up to 511 temporary mappings. In the above example, the kernel temporarily mapped the physical frame at 32 KiB to the virtual page at 0 KiB, indicated by the dashed arrow. Now the kernel can access the level 2 page table by writing to the page starting at 0 KiB. + + The process for accessing an arbitrary page table frame would be: + + - Search for a free entry in the identity mapped level 1 table. + - Store the physical address of the target frame in that entry. + - Access the target frame through the virtual page that maps to the entry. + - Set the entry back to unused. + + This approach keeps the virtual address space clean, since it reuses the same 512 virtual pages for creating the mappings. The drawback is that it is a bit cumbersome, especially since we would need to temporarily map up to three frames in order to create a single new mapping in the 4-level page table. + +- While both of the above approaches work, there is a third technique called **recursive page tables** that combines their advantages: It keeps all page table frames mapped like with the identity-mapping, so that no temporary mappings are needed, and also keeps the mapped pages together to avoid fragmentation of the virtual address space. Recursive page tables are described in detail in the following section, because this is the technique that we will use for our implementation. + +### Recursive Page Tables + +The idea behind this approach sounds simple: _Map some entry of the level 4 page table to the frame of the very same table_, similar to how the level 1 table in the previous example mapped itself. By doing this in the level 4 table, we effectively reserve a part of the virtual address space and map all current and future page table frames to that space. Thus, the single entry makes every table of every level accessible through a calculatable address. + +Let's go through an example to understand how this all works: + +![An example 4-level page hierarchy with each page table shown in physical memory. Entry 511 of the level 4 page is mapped to frame 4KiB, the frame of the level 4 table itself.](recursive-page-table.svg) + +The only difference to the [example at the beginning of this post] is the additional entry at index 511 in the level 4 table, which is mapped to physical frame 4 KiB, the frame of the level 4 table itself. + +[example at the beginning of this post]: #accessing-page-tables + +By letting the CPU follow this entry on a translation, it doesn't reach a level 3 table, but the same level 4 table again. This is similar to a recursive function that calls itself, therefore this table is called a _recursive page table_. The important thing is that the CPU assumes that every entry in the level 4 table points to a level 3 table, so it now treats the level 4 table as a level 3 table. This works because tables of all levels have the exact same layout on x86_64. + +By following the recursive entry one or multiple times before we start the actual translation, we can effectively shorten the number of levels that the CPU traverses. For example, if we follow the recursive entry once and then proceed to the level 3 table, the CPU thinks that the level 3 table is a level 2 table. Going further, it treats the level 2 table as a level 1 table, and the level 1 table as the mapped frame. This means that we can now read and write the level 1 page table because the CPU thinks that it is the mapped frame. + +TODO graphic + +Similarly, we can follow the recursive entry twice before starting the translation to reduce the number of traversed levels to two. Let's go through it step by step: First the CPU follows the recursive entry on the level 4 table and thinks that it reaches a level 3 table. Then it follows the recursive entry again and thinks that it reaches a level 2 table. But in reality, it is still on the level 4 table. When the CPU now follows another entry, it lands on a level 3 table, but thinks it is already on a level 1 table. So while the next entry points at a level 2 table, the CPU thinks that it points to the mapped frame, which allows us to read and write the level 2 table. + +TODO graphic + +Accessing the level 3 tables works in the same way. For accessing the level 3 table, we follow the recursive entry entry three times, tricking the CPU into thinking it is already on a level 1 table. Then we follow another entry and reach a level 3 table, which the CPU treats as a mapped frame. For accessing the level 4 table itself, we just follow the recursive entry four times until the CPU treats the level 4 table as mapped frame. + +TODO graphic + +#### Address Calculation + +We saw that we can access tables of all levels by following the recursive entry once or multiple times before the actual translation. But how do we do this? + +Remember, the indexes into the various table levels are derived directly from the virtual address: + +TODO graphic + +To follow the recursive entry once before doing the translation we move each of the address one entry to the right: + +TODO graphic + + + +## A Physical Memory Map + +## Allocating Stacks + +## Summary + +## What's next? + +--- +TODO update post date \ No newline at end of file diff --git a/blog/content/second-edition/posts/10-paging-2/recursive-page-table.svg b/blog/content/second-edition/posts/10-paging-2/recursive-page-table.svg new file mode 100644 index 00000000..1325ae5f --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/recursive-page-table.svg @@ -0,0 +1,2 @@ + +
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<div>32KiB</div> \ No newline at end of file From d87c41fa6c7ffbc09e28e59e9571986add7b2590 Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Sun, 6 Jan 2019 23:21:14 +0100 Subject: [PATCH 02/29] Continue second paging post --- .../second-edition/posts/10-paging-2/index.md | 156 +++++++++++++++--- .../posts/10-paging-2/qemu-bootinfo-print.png | Bin 0 -> 24012 bytes .../10-paging-2/qemu-print-p4-entries.png | Bin 0 -> 9480 bytes .../recursive-page-table-access-level-1.svg | 2 + .../recursive-page-table-access-level-2.svg | 2 + .../recursive-page-table-access-level-3.svg | 2 + ...indices-from-address-recursive-level-1.svg | 2 + ...indices-from-address-recursive-level-2.svg | 2 + ...indices-from-address-recursive-level-3.svg | 2 + ...indices-from-address-recursive-level-4.svg | 2 + 10 files changed, 149 insertions(+), 21 deletions(-) create mode 100644 blog/content/second-edition/posts/10-paging-2/qemu-bootinfo-print.png create mode 100644 blog/content/second-edition/posts/10-paging-2/qemu-print-p4-entries.png create mode 100644 blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-1.svg create mode 100644 blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-2.svg create mode 100644 blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-3.svg create mode 100644 blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-1.svg create mode 100644 blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-2.svg create mode 100644 blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-3.svg create mode 100644 blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-4.svg diff --git a/blog/content/second-edition/posts/10-paging-2/index.md b/blog/content/second-edition/posts/10-paging-2/index.md index 62295d35..17e19350 100644 --- a/blog/content/second-edition/posts/10-paging-2/index.md +++ b/blog/content/second-edition/posts/10-paging-2/index.md @@ -67,24 +67,24 @@ So in order access page table frames, we need to map some virtual pages to them. ![A virtual and a physical address space with an identity mapped level 1 table, which maps its 0th entry to the level 2 table frame, therey mapping that frame to page with address 0](temporarily-mapped-page-tables.svg) - The level 1 table in this graphic controls the first 2 MiB of the virtual address space. This is because it is reachable by starting at the CR3 register and following the 0th entry in the level 4, level 3, and level 2 page tables. The entry with index 8 maps the virtual page at address 32 KiB to the physical frame at address 32 KiB, thereby identity mapping the level 1 table it is contained in. The graphic shows this identity-mapping by the horizontal arrow at 32 KiB. + The level 1 table in this graphic controls the first 2 MiB of the virtual address space. This is because it is reachable by starting at the CR3 register and following the 0th entry in the level 4, level 3, and level 2 page tables. The entry with index 8 maps the virtual page at address 32 KiB to the physical frame at address 32 KiB, thereby identity mapping the level 1 table itself. The graphic shows this identity-mapping by the horizontal arrow at 32 KiB. - By writing the identity-mapped level 1 table our kernel can up to 511 temporary mappings. In the above example, the kernel temporarily mapped the physical frame at 32 KiB to the virtual page at 0 KiB, indicated by the dashed arrow. Now the kernel can access the level 2 page table by writing to the page starting at 0 KiB. + By writing to the identity-mapped level 1 table, our kernel can create up to 511 temporary mappings (512 minus the entry required for the identity mapping). In the above example, the kernel mapped the 0th entry of the level 1 table to the frame with address 24KiB. This created a temporary mapping of the virtual page at 0 KiB to the physical frame of the level 2 page table, indicated by the dashed arrow. Now the kernel can access the level 2 page table by writing to the page starting at 0 KiB. - The process for accessing an arbitrary page table frame would be: + The process for accessing an arbitrary page table frame with temporary mappings would be: - Search for a free entry in the identity mapped level 1 table. - - Store the physical address of the target frame in that entry. + - Map that entry to the physical frame of the page table that we want to access. - Access the target frame through the virtual page that maps to the entry. - - Set the entry back to unused. + - Set the entry back to unused thereby removing the temporary mapping again. - This approach keeps the virtual address space clean, since it reuses the same 512 virtual pages for creating the mappings. The drawback is that it is a bit cumbersome, especially since we would need to temporarily map up to three frames in order to create a single new mapping in the 4-level page table. + This approach keeps the virtual address space clean, since it reuses the same 512 virtual pages for creating the mappings. The drawback is that it is a bit cumbersome, especially since a new mapping might require modifications of multiple table levels, which means that we would need to repeat the above process multiple times. -- While both of the above approaches work, there is a third technique called **recursive page tables** that combines their advantages: It keeps all page table frames mapped like with the identity-mapping, so that no temporary mappings are needed, and also keeps the mapped pages together to avoid fragmentation of the virtual address space. Recursive page tables are described in detail in the following section, because this is the technique that we will use for our implementation. +- While both of the above approaches work, there is a third technique called **recursive page tables** that combines their advantages: It keeps all page table frames mapped like with the identity-mapping, so that no temporary mappings are needed, and also keeps the mapped pages together to avoid fragmentation of the virtual address space. This is the technique that we will use for our implementation, therefore it is described in detail in the following section. -### Recursive Page Tables +## Recursive Page Tables -The idea behind this approach sounds simple: _Map some entry of the level 4 page table to the frame of the very same table_, similar to how the level 1 table in the previous example mapped itself. By doing this in the level 4 table, we effectively reserve a part of the virtual address space and map all current and future page table frames to that space. Thus, the single entry makes every table of every level accessible through a calculatable address. +The idea behind this approach sounds simple: _Map some entry of the level 4 page table to the frame of level 4 table itself_, similar to how the level 1 table in the previous example mapped itself. By doing this in the level 4 table, we effectively reserve a part of the virtual address space and map all current and future page table frames to that space. Thus, the single entry makes every table of every level accessible through a calculatable address. Let's go through an example to understand how this all works: @@ -96,29 +96,143 @@ The only difference to the [example at the beginning of this post] is the additi By letting the CPU follow this entry on a translation, it doesn't reach a level 3 table, but the same level 4 table again. This is similar to a recursive function that calls itself, therefore this table is called a _recursive page table_. The important thing is that the CPU assumes that every entry in the level 4 table points to a level 3 table, so it now treats the level 4 table as a level 3 table. This works because tables of all levels have the exact same layout on x86_64. -By following the recursive entry one or multiple times before we start the actual translation, we can effectively shorten the number of levels that the CPU traverses. For example, if we follow the recursive entry once and then proceed to the level 3 table, the CPU thinks that the level 3 table is a level 2 table. Going further, it treats the level 2 table as a level 1 table, and the level 1 table as the mapped frame. This means that we can now read and write the level 1 page table because the CPU thinks that it is the mapped frame. +By following the recursive entry one or multiple times before we start the actual translation, we can effectively shorten the number of levels that the CPU traverses. For example, if we follow the recursive entry once and then proceed to the level 3 table, the CPU thinks that the level 3 table is a level 2 table. Going further, it treats the level 2 table as a level 1 table, and the level 1 table as the mapped frame. This means that we can now read and write the level 1 page table because the CPU thinks that it is the mapped frame. The graphic below illustrates the 5 translation steps: -TODO graphic +![The above example 4-level page hierarchy with 5 arrows: "Step 0" from CR4 to level 4 table, "Step 1" from level 4 table to level 4 table, "Step 2" from level 4 table to level 3 table, "Step 3" from level 3 table to level 2 table, and "Step 4" from level 2 table to level 1 table.](recursive-page-table-access-level-1.svg) -Similarly, we can follow the recursive entry twice before starting the translation to reduce the number of traversed levels to two. Let's go through it step by step: First the CPU follows the recursive entry on the level 4 table and thinks that it reaches a level 3 table. Then it follows the recursive entry again and thinks that it reaches a level 2 table. But in reality, it is still on the level 4 table. When the CPU now follows another entry, it lands on a level 3 table, but thinks it is already on a level 1 table. So while the next entry points at a level 2 table, the CPU thinks that it points to the mapped frame, which allows us to read and write the level 2 table. +Similarly, we can follow the recursive entry twice before starting the translation to reduce the number of traversed levels to two: -TODO graphic +![The same 4-level page hierarchy with the following 4 arrows: "Step 0" from CR4 to level 4 table, "Steps 1&2" from level 4 table to level 4 table, "Step 3" from level 4 table to level 3 table, and "Step 4" from level 3 table to level 2 table.](recursive-page-table-access-level-2.svg) -Accessing the level 3 tables works in the same way. For accessing the level 3 table, we follow the recursive entry entry three times, tricking the CPU into thinking it is already on a level 1 table. Then we follow another entry and reach a level 3 table, which the CPU treats as a mapped frame. For accessing the level 4 table itself, we just follow the recursive entry four times until the CPU treats the level 4 table as mapped frame. +Let's go through it step by step: First the CPU follows the recursive entry on the level 4 table and thinks that it reaches a level 3 table. Then it follows the recursive entry again and thinks that it reaches a level 2 table. But in reality, it is still on the level 4 table. When the CPU now follows a different entry, it lands on a level 3 table, but thinks it is already on a level 1 table. So while the next entry points at a level 2 table, the CPU thinks that it points to the mapped frame, which allows us to read and write the level 2 table. -TODO graphic +Accessing the tables of levels 3 and 4 works in the same way. For accessing the level 3 table, we follow the recursive entry entry three times, tricking the CPU into thinking it is already on a level 1 table. Then we follow another entry and reach a level 3 table, which the CPU treats as a mapped frame. For accessing the level 4 table itself, we just follow the recursive entry four times until the CPU treats the level 4 table itself as mapped frame (in blue in the graphic below). -#### Address Calculation +![The same 4-level page hierarchy with the following 3 arrows: "Step 0" from CR4 to level 4 table, "Steps 1,2,3" from level 4 table to level 4 table, and "Step 4" from level 4 table to level 3 table. In blue the alternative "Steps 1,2,3,4" arrow from level 4 table to level 4 table.](recursive-page-table-access-level-3.svg) -We saw that we can access tables of all levels by following the recursive entry once or multiple times before the actual translation. But how do we do this? +It might take some time to wrap your head around the concept, but it works quite well in practice. -Remember, the indexes into the various table levels are derived directly from the virtual address: +### Address Calculation -TODO graphic +We saw that we can access tables of all levels by following the recursive entry once or multiple times before the actual translation. Since the indexes into the tables of the four levels are derived directly from the virtual address, we need to construct special virtual addresses for this technique. Remember, the page table indexes are derived from the address in the following way: -To follow the recursive entry once before doing the translation we move each of the address one entry to the right: +![Bits 0–12 are the page offset, bits 12–21 the level 1 index, bits 21–30 the level 2 index, bits 30–39 the level 3 index, and bits 39–48 the level 4 index](../paging/x86_64-table-indices-from-address.svg) -TODO graphic +Let's assume that we want to access the level 1 page table that maps a specific page. As we learned above, this means that we have to follow the recursive entry one time before continuing with the level 4, level 3, and level 2 indexes. To do that we move each block of the address one block to the right and use the set the original level 4 index to the index of the recursive entry: + +![Bits 0–12 are the offset into the level 1 table frame, bits 12–21 the level 2 index, bits 21–30 the level 3 index, bits 30–39 the level 4 index, and bits 39–48 the index of the recursive entry](table-indices-from-address-recursive-level-1.svg) + +For accessing the level 2 table of that page, we move each index block two blocks to the right and set both the blocks of the level 4 index and the level 3 index to the index of the recursive entry: + +![Bits 0–12 are the offset into the level 2 table frame, bits 12–21 the level 3 index, bits 21–30 the level 4 index, and bits 30–39 and bits 39–48 are the index of the recursive entry](table-indices-from-address-recursive-level-2.svg) + +Accessing the level 3 table works by moving each block three blocks to the right and using the recursive index for the level 4, level 3, and level 2 address blocks: + +![Bits 0–12 are the offset into the level 3 table frame, bits 12–21 the level 4 index, and bits 21–30, bits 30–39 and bits 39–48 are the index of the recursive entry](table-indices-from-address-recursive-level-3.svg) + +Finally, we can access the level 4 table by moving each block four blocks to the right and using the recursive index for all address blocks except for the offset: + +![Bits 0–12 are the offset into the level l table frame and bits 12–21, bits 21–30, bits 30–39 and bits 39–48 are the index of the recursive entry](table-indices-from-address-recursive-level-4.svg) + +The page table index blocks are 9 bits, so moving each block one block to the right means a bitshift by 9 bits: `address >> 9`. To derive the 12-bit offset field from the shifted index, we need to multiply it by 8, the size of a page table entry. Through this operation, we can calculate addresses for accessing all four page tables in the mapping of each page. + +The table below summarizes the address structure for accessing the different kinds of frames: + +Mapped Frame for | Address Structure ([octal]) +---------------- | ------------------------------- +Page | `0o_SSSSSS_AAA_BBB_CCC_DDD_EEEE` +Level 1 Table | `0o_SSSSSS_RRR_AAA_BBB_CCC_DDDD` +Level 2 Table | `0o_SSSSSS_RRR_RRR_AAA_BBB_CCCC` +Level 3 Table | `0o_SSSSSS_RRR_RRR_RRR_AAA_BBBB` +Level 4 Table | `0o_SSSSSS_RRR_RRR_RRR_RRR_AAAA` + +[octal]: https://en.wikipedia.org/wiki/Octal + +Whereas `AAA` is the level 4 index, `BBB` the level 3 index, `CCC` the level 2 index, `DDD` the level 1 index, and `EEEE` the offset into the mapped frame. `RRR` is the index of the recursive entry. When an index (three digits) is transformed to an offset (four digits), it is done by multiplying it by 8 (the size of a page table entry). With this offset, the resulting address directly points to the respective page table entry. + +`SSSSSS` are sign extension bits, which means that they are all copies of bit 47. This is a special requirement for valid addresses on the x86_64 architecture. We explained it in the [previous post][sign extension]. + +[sign extension]: ./second-edition/posts/09-paging/index.md#paging-on-x86 + +## Implementation + +After all this theory we can finally start our implementation. As already mentioned, our kernel already runs on a page tables created by the bootloader. The bootloader also set up a recursive mapping for us, so we already can use addresses with the above structure to access the page tables. The only missing thing that we don't know is which entry is mapped recursively. + +### Boot Information + +To communicate the index of the recursive entry and other information to our kernel, the bootloader passes a reference to a boot information structure as an argument when calling our `_start` function. Right now we don't have this argument declared in our function, so let's add it: + +```rust +// in src/main.rs + +use bootloader::bootinfo::BootInfo; + +#[cfg(not(test))] +#[no_mangle] +pub extern "C" fn _start(boot_info: &'static BootInfo) -> ! { + println!("Hello World{}", "!"); + println!("boot_info: {:x?}", boot_info); + + […] +} +``` + +The [`BootInfo`] struct is still in an early stage, so expect some breakage in newer bootloader versions. When we print it, we see that it currently has the three fields `p4_table_addr`, `memory_map`, and `package`: + +[`BootInfo`]: https://docs.rs/bootloader/0.3.11/bootloader/bootinfo/struct.BootInfo.html + +![QEMU printing a `BootInfo` struct: "boot_info: Bootlnfo { p4_table_addr: fffffffffffff000. memory_map: […]. package: […]"](qemu-bootinfo-print.png) + +The most interesting field for us right now is `p4_table_addr`, as it contains a virtual address that is mapped to the physical frame of the level 4 page table. As we see this address is `0xfffffffffffff000`, which indicates a recursive address with the recursive index 511. + +The `memory_map` field will become relevant later in this post. The `package` field is an in-progress feature to bundle additional data with the bootloader. The implementation is not finished, so we can ignore this field for now. + +### Accessing the Level 4 Page Table + +We can now try to access the level 4 page table: + +```rust +// inside our `_start` function + +[…] + +let level_4_table_pointer = boot_info.p4_table_addr as *const u64; + +let entry_0 = unsafe { *level_4_table_pointer }; +println!("Entry 0: {:#x}", entry_0); + +let entry_1 = unsafe { *level_4_table_pointer.offset(1) }; +println!("Entry 1: {:#x}", entry_1); + +let entry_2 = unsafe { *level_4_table_pointer.offset(2) }; +println!("Entry 2: {:#x}", entry_2); + +let entry_511 = unsafe { *level_4_table_pointer.offset(511) }; +println!("Entry 511: {:#x}", entry_511); + +[…] +``` + +This code casts the `p4_table_addr` to a pointer to an `u64`. As we saw in the [previous post][page table format], each page table entry is 8 bytes (64 bits), so an `u64` represents exactly one entry. We use unsafe blocks to read from the raw pointers and the [`offset` method] to perform pointer arithmetic. When we run it, we see the following output: + +[page table format]: ./second-edition/posts/09-paging/index.md##page-table-format +[`offset` method]: https://doc.rust-lang.org/std/primitive.pointer.html#method.offset + +![QEMU printing "Hello world! Entry 0: 0x2023 Entry 1: 0x6d8063 Entry 2: 0x0 Entry 511: 0x1063 It did not crash!](qemu-print-p4-entries.png) + +When we look at the [format of page table entries][page table format], we see that the value `0x2023` of entry 0 means that the entry is `present`, `writable`, was `accessed` by the CPU, and is mapped to frame `0x2000`. Entry 1 is mapped to frame `0x6d8000` has the same flags as entry 0, with the addition of the `dirty` flag that indicates that the page was written. + +Entry 2 is not `present`, so this virtual address range is not mapped to any physical addresses. Entry 511 is mapped to frame `0x1000` with the same flags as entry 1. This is the recursive entry, which means that `0x1000` is the physical frame that contains the level 4 page table. + +### Page Table Types + +While accessing the page tables through raw pointers is possible, it is cumbersome and requires many uses of `unsafe`. Like always we want to avoid that by creating safe abstractions. + +TODO x86_64 PageTable type + +TODO directly pass &PageTable in boot_info? + +TODO introduce boot_info earlier? diff --git a/blog/content/second-edition/posts/10-paging-2/qemu-bootinfo-print.png b/blog/content/second-edition/posts/10-paging-2/qemu-bootinfo-print.png new file mode 100644 index 0000000000000000000000000000000000000000..83efc17ab386df78043c76eccf40617d89cb465d GIT binary patch literal 24012 zcmeAS@N?(olHy`uVBq!ia0y~yV7kP>z_^x!je&u|`rBk>1_lO}VkgfK4h{~E8jh3> z1_lO+64!{5;QX|b^2DN4hTO!GRNdm_qSVy9;*9)~6VpC;F)%1Fc)B=-RLpsMw|axh z&Da}1-Q^Pym=*Wz5VZ&S6`>uY}&>0>iTch zYgg^FfBbsH{jR3<_v_R3R?iFE<>Iy)wmZ)ce|GDeG4J=xpR$!#eb)Yp(fRBZ%l$hj z=zrB~?S)DJjTkh<6?O&JQetpU=)w}Fc z^E~C-KaAREE_>tu|N8XFp?e%Ax|a%lJ+vTWnXT*H*YdSr3C#w11_p)&{hPoV z-|f~fjpb)xVE7U-@A;(EnL1+Jkx#fI&lI0bEiB3`(o>q5a`V-1yO~cazkaU^>wjKZ zH|zb|Bj0M$Ht$@uZgHTRvgFB(IVUqrCS5%7_r|Bq=kHDEz0AeLz`!8)$!5CE`P6+8 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a/blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-1.svg b/blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-1.svg new file mode 100644 index 00000000..a151a767 --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-1.svg @@ -0,0 +1,2 @@ + +
Physical Memory
Physical Memory
0KiB
[Not supported by viewer]
Level 4 Page Table
Level 4 Page Table
4KiB
[Not supported by viewer]
IndexFrameFlags
024KiB
r/w
…


[Not supported by viewer]
Level 3 Page Table
Level 3 Page Table
16KiB
<div>16KiB</div>
24KiB
<div>24KiB</div>
8KiB
[Not supported by viewer]
IndexFrameFlags
…


511
24KiB
r/w
[Not supported by viewer]
Level 2 Page Table
Level 2 Page Table
Level 1 Page Table
Level 1 Page Table
32KiB
<div>32KiB</div>
IndexFrameFlags
036KiB
r/w
…


127
12KiBr
…

[Not supported by viewer]
4KiB
4KiB
CR3 Register
CR3 Register
IndexFrameFlags
0-
-
1
16KiB
r/w
…


511
4KiB
r/w
[Not supported by viewer]
Step 0
Step 0
Step 1
Step 1
Step 2
Step 2
Step 3
Step 3
Step 4
Step 4 \ No newline at end of file diff --git a/blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-2.svg b/blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-2.svg new file mode 100644 index 00000000..e28ab42d --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-2.svg @@ -0,0 +1,2 @@ + +
Physical Memory
Physical Memory
0KiB
[Not supported by viewer]
Level 4 Page Table
Level 4 Page Table
4KiB
[Not supported by viewer]
IndexFrameFlags
024KiB
r/w
…


[Not supported by viewer]
Level 3 Page Table
Level 3 Page Table
16KiB
<div>16KiB</div>
24KiB
<div>24KiB</div>
8KiB
[Not supported by viewer]
IndexFrameFlags
…


511
24KiB
r/w
[Not supported by viewer]
Level 2 Page Table
Level 2 Page Table
Level 1 Page Table
Level 1 Page Table
32KiB
<div>32KiB</div>
IndexFrameFlags
036KiB
r/w
…


127
12KiBr
…

[Not supported by viewer]
4KiB
4KiB
CR3 Register
CR3 Register
IndexFrameFlags
0-
-
1
16KiB
r/w
…


511
4KiB
r/w
[Not supported by viewer]
Step 0
Step 0
Steps 1&2
Steps 1&2
Step 3
Step 3
Step 4
Step 4 \ No newline at end of file diff --git a/blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-3.svg b/blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-3.svg new file mode 100644 index 00000000..50a32a4e --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/recursive-page-table-access-level-3.svg @@ -0,0 +1,2 @@ + +
Physical Memory
Physical Memory
0KiB
[Not supported by viewer]
Level 4 Page Table
Level 4 Page Table
4KiB
[Not supported by viewer]
IndexFrameFlags
024KiB
r/w
…


[Not supported by viewer]
Level 3 Page Table
Level 3 Page Table
16KiB
<div>16KiB</div>
24KiB
<div>24KiB</div>
8KiB
[Not supported by viewer]
IndexFrameFlags
…


511
24KiB
r/w
[Not supported by viewer]
Level 2 Page Table
Level 2 Page Table
Level 1 Page Table
Level 1 Page Table
32KiB
<div>32KiB</div>
IndexFrameFlags
036KiB
r/w
…


127
12KiBr
…

[Not supported by viewer]
4KiB
4KiB
CR3 Register
CR3 Register
IndexFrameFlags
0-
-
1
16KiB
r/w
…


511
4KiB
r/w
[Not supported by viewer]
Step 0
Step 0
Steps 1,2,3
Steps 1,2,3
Step 4
Step 4
Steps 1,2,3,4
Steps 1,2,3,4 \ No newline at end of file diff --git a/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-1.svg b/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-1.svg new file mode 100644 index 00000000..95f36c3b --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-1.svg @@ -0,0 +1,2 @@ + +
64
[Not supported by viewer]
0
[Not supported by viewer]
12
[Not supported by viewer]
21
21
30
[Not supported by viewer]
39
39
48
48
Index of Recursive Level 4 Entry
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Level 4
Index
[Not supported by viewer]
Level 3
Index
[Not supported by viewer]
Level 2
Index
[Not supported by viewer]
Offset into Level 1 Page Table Frame
Offset into Level 1 Page Table Frame \ No newline at end of file diff --git a/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-2.svg b/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-2.svg new file mode 100644 index 00000000..9443213f --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-2.svg @@ -0,0 +1,2 @@ + +
64
[Not supported by viewer]
0
[Not supported by viewer]
12
[Not supported by viewer]
21
21
30
[Not supported by viewer]
39
39
48
48
Index of Recursive Level 4 Entry
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Index of Recursive Level 4 Entry
<div>Index of Recursive Level 4 Entry</div>
Level 4
Index
[Not supported by viewer]
Level 3
Index
[Not supported by viewer]
Offset into Level 2 Page Table Frame
Offset into Level 2 Page Table Frame \ No newline at end of file diff --git a/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-3.svg b/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-3.svg new file mode 100644 index 00000000..28b55b8b --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-3.svg @@ -0,0 +1,2 @@ + +
64
[Not supported by viewer]
0
[Not supported by viewer]
12
[Not supported by viewer]
21
21
30
[Not supported by viewer]
39
39
48
48
Index of Recursive Level 4 Entry
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Index of Recursive Level 4 Entry
<div>Index of Recursive Level 4 Entry</div>
Index of Recursive Level 4 Entry
<div>Index of Recursive Level 4 Entry</div>
Level 4
Index
[Not supported by viewer]
Offset into Level 3 Page Table Frame
Offset into Level 3 Page Table Frame \ No newline at end of file diff --git a/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-4.svg b/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-4.svg new file mode 100644 index 00000000..8b06a77d --- /dev/null +++ b/blog/content/second-edition/posts/10-paging-2/table-indices-from-address-recursive-level-4.svg @@ -0,0 +1,2 @@ + +
64
[Not supported by viewer]
0
[Not supported by viewer]
12
[Not supported by viewer]
21
21
30
[Not supported by viewer]
39
39
48
48
Index of Recursive Level 4 Entry
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Index of Recursive Level 4 Entry
<div>Index of Recursive Level 4 Entry</div>
Index of Recursive Level 4 Entry
<div>Index of Recursive Level 4 Entry</div>
Index of Recursive Level 4 Entry
<div>Index of Recursive Level 4 Entry</div>
Offset into Level 4 Page Table Frame
Offset into Level 4 Page Table Frame \ No newline at end of file From abd5082c569f6a65950beb9f0dd840875d894d52 Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Sun, 6 Jan 2019 23:21:37 +0100 Subject: [PATCH 03/29] Add second paging post to index page --- blog/templates/second-edition/index.html | 1 + 1 file changed, 1 insertion(+) diff --git a/blog/templates/second-edition/index.html b/blog/templates/second-edition/index.html index adafd4fa..ee1640f4 100644 --- a/blog/templates/second-edition/index.html +++ b/blog/templates/second-edition/index.html @@ -44,6 +44,7 @@
Memory Management
{{ macros::post_link(page=posts.8) }} + {{ macros::post_link(page=posts.9) }}
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zq@%6{8i_F+FyFkHD|7RV<=+bS+Q+Z|{_{qmeBX?3=}Zh2dn~k;m>0=Dm|S}ycX3~= zSHY?Z>#INKoU}-PeIt49tF88T-k Date: Fri, 18 Jan 2019 13:54:59 +0100 Subject: [PATCH 12/29] Various minor improvements to post --- .../posts/10-advanced-paging/index.md | 39 +++++++++++-------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/blog/content/second-edition/posts/10-advanced-paging/index.md b/blog/content/second-edition/posts/10-advanced-paging/index.md index 3c617c58..94b54ef6 100644 --- a/blog/content/second-edition/posts/10-advanced-paging/index.md +++ b/blog/content/second-edition/posts/10-advanced-paging/index.md @@ -17,13 +17,13 @@ This blog is openly developed on [Github]. If you have any problems or questions ## Introduction -In the [previous post] we learned about the principles of paging and how the 4-level page tables on the x86_64 architecture work. We also found out that the bootloader already set up a 4-level page table hierarchy for our kernel, since paging is mandatory on x86_64 in 64-bit mode. This means that our kernel already runs on virtual addresses. +In the [previous post] we learned about the principles of paging and how the 4-level page tables on the x86_64 architecture work. We also found out that the bootloader already set up a 4-level page table hierarchy for our kernel, which means that our kernel already runs on virtual addresses. This improves safety since illegal memory accesses cause page fault exceptions instead of modifying arbitrary physical memory. [previous post]: ./second-edition/posts/09-paging-introduction/index.md -The problem that page tables use physical addresses internally, which we can't access directly from our kernel. We experienced that problem already [at the end of the previous post] when we tried to inspect the active page tables. The next section discusses the problem in detail and provides different approaches to a solution. +However, it also causes a problem when we try to access the page tables from our kernel, because we can't directly access the physical addresses that are stored in page table entries or the `CR3` register. We experienced that problem already [at the end of the previous post] when we tried to inspect the active page tables. The next section discusses the problem in detail and provides different approaches to a solution. -[at the end of the previous post]: ./second-edition/posts/09-paging-introduction/index.md#try-it-out +[at the end of the previous post]: ./second-edition/posts/09-paging-introduction/index.md#accessing-the-page-tables ## Accessing Page Tables @@ -44,7 +44,7 @@ So in order access page table frames, we need to map some virtual pages to them. In this example we see various identity-mapped page table frames. This way the physical addresses in the page tables are also valid virtual addresses, so that we can easily access the page tables of all levels starting from the CR3 register. - However, it clutters the virtual address space and makes it more difficult to find continuous memory regions of larger sizes. For example, imagine that we want to create a virtual memory region of size 1000 KiB in the above graphic, e.g. for [memory-mapping a file]. We can't start the region at `26 KiB` because it would collide with the already mapped page at `1004 MiB`. So we have to look further until we find a large enough unmapped area, for example at `1008 KiB`. This is a similar fragmentation problem as with [segmentation]. + However, it clutters the virtual address space and makes it more difficult to find continuous memory regions of larger sizes. For example, imagine that we want to create a virtual memory region of size 1000 KiB in the above graphic, e.g. for [memory-mapping a file]. We can't start the region at `28 KiB` because it would collide with the already mapped page at `1004 MiB`. So we have to look further until we find a large enough unmapped area, for example at `1008 KiB`. This is a similar fragmentation problem as with [segmentation]. [memory-mapping a file]: https://en.wikipedia.org/wiki/Memory-mapped_file [segmentation]: ./second-edition/posts/09-paging-introduction/index.md#fragmentation @@ -122,17 +122,17 @@ Finally, we can access the level 4 table by moving each block four blocks to the ![Bits 0–12 are the offset into the level l table frame and bits 12–21, bits 21–30, bits 30–39 and bits 39–48 are the index of the recursive entry](table-indices-from-address-recursive-level-4.svg) -The page table index blocks are 9 bits, so moving each block one block to the right means a bitshift by 9 bits: `address >> 9`. To derive the 12-bit offset field from the shifted index, we need to multiply it by 8, the size of a page table entry. Through this operation, we can calculate virtual addresses for the page tables of all four levels. +We can now calculate virtual addresses for the page tables of all four levels. We can even calculate an address that points exactly to a specific page table entry by multiplying the its index by 8, the size of a page table entry. The table below summarizes the address structure for accessing the different kinds of frames: -Mapped Frame for | Address Structure ([octal]) ----------------- | ------------------------------- -Page | `0o_SSSSSS_AAA_BBB_CCC_DDD_EEEE` -Level 1 Table | `0o_SSSSSS_RRR_AAA_BBB_CCC_DDDD` -Level 2 Table | `0o_SSSSSS_RRR_RRR_AAA_BBB_CCCC` -Level 3 Table | `0o_SSSSSS_RRR_RRR_RRR_AAA_BBBB` -Level 4 Table | `0o_SSSSSS_RRR_RRR_RRR_RRR_AAAA` +Virtual Address for | Address Structure ([octal]) +------------------- | ------------------------------- +Page | `0o_SSSSSS_AAA_BBB_CCC_DDD_EEEE` +Level 1 Table Entry | `0o_SSSSSS_RRR_AAA_BBB_CCC_DDDD` +Level 2 Table Entry | `0o_SSSSSS_RRR_RRR_AAA_BBB_CCCC` +Level 3 Table Entry | `0o_SSSSSS_RRR_RRR_RRR_AAA_BBBB` +Level 4 Table Entry | `0o_SSSSSS_RRR_RRR_RRR_RRR_AAAA` [octal]: https://en.wikipedia.org/wiki/Octal @@ -142,6 +142,8 @@ Whereas `AAA` is the level 4 index, `BBB` the level 3 index, `CCC` the level 2 i [sign extension]: ./second-edition/posts/09-paging-introduction/index.md#paging-on-x86 +We use [octal] numbers for representing the addresses since each octal character represents 3 bits, which allows us to clearly spearate the the 9-bit indexes of the different page table levels. This isn't possible with the hexadecimal system where each character represents four bits. + ## Implementation After all this theory we can finally start our implementation. Conveniently, the bootloader not only created page tables for our kernel, it also created a recursive mapping in the last entry of the level 4 table. The bootloader did this, because otherwise there would be a [chicken or egg problem]: We need to access the level 4 table to create a recursive mapping, but we can't access it without some kind of mapping. @@ -219,7 +221,9 @@ First, we calculate the page table indices and the page offset from the address ![Bits 0–12 are the page offset, bits 12–21 the level 1 index, bits 21–30 the level 2 index, bits 30–39 the level 3 index, and bits 39–48 the level 4 index](../paging-introduction/x86_64-table-indices-from-address.svg) -Then we transform the `level_4_table_addr` to a `&PageTable`, which is an `unsafe` operation since the compiler can't know that the address is valid. We use the indexing operator to look at the entry with `level_4_index`. If that entry is null, there is no level 3 table for this level 4 entry, which means that the `addr` is not mapped to any physical memory, so we return `None`. +Then we transform the `level_4_table_addr` to a [`PageTable`] reference, which is an `unsafe` operation since the compiler can't know that the address is valid. We use the indexing operator to look at the entry with `level_4_index`. If that entry is null, there is no level 3 table for this level 4 entry, which means that the `addr` is not mapped to any physical memory, so we return `None`. + +[`PageTable`]: https://docs.rs/x86_64/0.3.5/x86_64/structures/paging/struct.PageTable.html If the entry is not `None`, we know that a level 3 table exist. We calculate the virtual address of it by shifting the level 4 address 9 bits to the left and setting the address bits 12–21 to the level 4 index (see the section about [address calculation]). We can do that because the recursive index is `0o777`, so that it is also a valid sign extension. We then do the same cast and entry-checking as with the level 4 table. @@ -227,7 +231,7 @@ If the entry is not `None`, we know that a level 3 table exist. We calculate the After we checked the three higher level pages, we can finally read the entry of the level 1 table that tells us the physical frame that the address is mapped to. As a last step, we add the page offset to that address and return it. -If we knew that the address is mapped, we could directly access the level 1 table without looking at the higher level pages first. But since we don't know this, so we have to check whether the level 1 table exists first, otherwise we would cause a page fault for unmapped addresses. +If we knew that the address is mapped, we could directly access the level 1 table without looking at the higher level pages first. But since we don't know this, we have to check whether the level 1 table exists first, otherwise we would cause a page fault for unmapped addresses. #### Try it out @@ -336,8 +340,6 @@ After reading the page tables and creating a translation function, the next step The difficulty of creating a new mapping depends on on the virtual page that we want to map. In the easiest case, the level 1 page table for the page already exists and we just need to write a single entry. In the most difficult case, the page is in a memory region for that no level 3 exists yet, so that we need to create new level 3, level 2 and level 1 page tables first. -For creating a new page table we need to find an unused physical frame where the page table will be stored. We initialize it to zero and create a mapping for that frame in the higher level page table. At this point, we can access the new page table through the recursive page table and continue with the next level. - Let's start with the simple case and assume that we don't need to create new page tables. The bootloader loads itself in the first megabyte of the virtual address space, so we know that a valid level 1 table exists for this region. We can choose any unused page in this memory region for our example mapping, for example the page at address `0x1000`. As the target frame we use `0xb8000`, the frame of the VGA text buffer. This way we can easily test whether our mapping worked. We implement it in a new `create_mapping` function in our `memory` module: @@ -614,6 +616,9 @@ Now the mapping succeeds and we see the white block on the screen again: The `map_to` method was now able to create the missing page tables on the frames allocated from our `BootInfoFrameAllocator`. You can insert a `println` message into the `BootInfoFrameAllocator::alloc` method to see how it's called. +For creating a new page table we need to find an unused physical frame where the page table will be stored. We initialize it to zero and create a mapping for that frame in the higher level page table. At this point, we can access the new page table through the recursive page table and continue with the next level. + + We're now able to map arbitrary pages and to allocate new physical frames when we need them. # TODO @@ -626,4 +631,6 @@ We're now able to map arbitrary pages and to allocate new physical frames when w --- TODO spellcheck +TODO improve transition between sections TODO update post date +TODO check level 2 table diagram 24KiB -> 32KiB \ No newline at end of file From 4cec9642ab823ee3a7cbb53e8207f1ffed1de831 Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Fri, 25 Jan 2019 18:10:01 +0100 Subject: [PATCH 13/29] Update from gutenberg to zola --- blog/content/second-edition/posts/10-advanced-paging/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/blog/content/second-edition/posts/10-advanced-paging/index.md b/blog/content/second-edition/posts/10-advanced-paging/index.md index 94b54ef6..8ceb444e 100644 --- a/blog/content/second-edition/posts/10-advanced-paging/index.md +++ b/blog/content/second-edition/posts/10-advanced-paging/index.md @@ -1,6 +1,6 @@ +++ title = "Advanced Paging" -order = 10 +weight = 10 path = "advanced-paging" date = 0000-01-01 template = "second-edition/page.html" From 660528bb52911f2c193befcc55f1792186170105 Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Fri, 25 Jan 2019 19:20:54 +0100 Subject: [PATCH 14/29] Minor rewordings --- .../second-edition/posts/10-advanced-paging/index.md | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/blog/content/second-edition/posts/10-advanced-paging/index.md b/blog/content/second-edition/posts/10-advanced-paging/index.md index 8ceb444e..5a1d5d78 100644 --- a/blog/content/second-edition/posts/10-advanced-paging/index.md +++ b/blog/content/second-edition/posts/10-advanced-paging/index.md @@ -17,14 +17,16 @@ This blog is openly developed on [Github]. If you have any problems or questions ## Introduction -In the [previous post] we learned about the principles of paging and how the 4-level page tables on the x86_64 architecture work. We also found out that the bootloader already set up a 4-level page table hierarchy for our kernel, which means that our kernel already runs on virtual addresses. This improves safety since illegal memory accesses cause page fault exceptions instead of modifying arbitrary physical memory. +In the [previous post] we learned about the principles of paging and how the 4-level page tables on x86_64 work. We also found out that the bootloader already set up a page table hierarchy for our kernel, which means that our kernel already runs on virtual addresses. This improves safety since illegal memory accesses cause page fault exceptions instead of modifying arbitrary physical memory. [previous post]: ./second-edition/posts/09-paging-introduction/index.md -However, it also causes a problem when we try to access the page tables from our kernel, because we can't directly access the physical addresses that are stored in page table entries or the `CR3` register. We experienced that problem already [at the end of the previous post] when we tried to inspect the active page tables. The next section discusses the problem in detail and provides different approaches to a solution. +However, it also causes a problem when we try to access the page tables from our kernel, because we can't directly access the physical addresses that are stored in page table entries or the `CR3` register. We experienced that problem already [at the end of the previous post] when we tried to inspect the active page tables. [at the end of the previous post]: ./second-edition/posts/09-paging-introduction/index.md#accessing-the-page-tables +The next section discusses the problem in detail and provides different approaches to a solution. Afterwards, we will implement a function to translate virtual to physical addresses and learn how to create new mappings in the page tables. + ## Accessing Page Tables Accessing the page tables from our kernel is not as easy as it may seem. To understand the problem let's take a look at the example 4-level page table hierarchy of the previous post again: @@ -35,14 +37,14 @@ The important thing here is that each page entry stores the _physical_ address o The problem for us is that we can't directly access physical addresses from our kernel, since our kernel also runs on top of virtual addresses. For example when we access address `4 KiB`, we access the _virtual_ address `4 KiB`, not the _physical_ address `4 KiB` where the level 4 page table lives. When we want to acccess the physical address `4 KiB`, we can only do so through some virtual address that maps to it. -So in order access page table frames, we need to map some virtual pages to them. There are different ways to create these mappings that all allow us to access arbitrary page table frames: +So in order to access page table frames, we need to map some virtual pages to them. There are different ways to create these mappings that all allow us to access arbitrary page table frames: - A simple solution is to **identity map all page tables**: ![A virtual and a physical address space with various virtual pages mapped to the physical frame with the same address](identity-mapped-page-tables.svg) - In this example we see various identity-mapped page table frames. This way the physical addresses in the page tables are also valid virtual addresses, so that we can easily access the page tables of all levels starting from the CR3 register. + In this example we see various identity-mapped page table frames. This way the physical addresses of page tables are also valid virtual addresses, so that we can easily access the page tables of all levels starting from the CR3 register. However, it clutters the virtual address space and makes it more difficult to find continuous memory regions of larger sizes. For example, imagine that we want to create a virtual memory region of size 1000 KiB in the above graphic, e.g. for [memory-mapping a file]. We can't start the region at `28 KiB` because it would collide with the already mapped page at `1004 MiB`. So we have to look further until we find a large enough unmapped area, for example at `1008 KiB`. This is a similar fragmentation problem as with [segmentation]. From 7cb62ee7fe18c8680529a855c52c5535bb139b6f Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Fri, 25 Jan 2019 19:21:21 +0100 Subject: [PATCH 15/29] Make `Recursive Page Tables` a subsection --- blog/content/second-edition/posts/10-advanced-paging/index.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/blog/content/second-edition/posts/10-advanced-paging/index.md b/blog/content/second-edition/posts/10-advanced-paging/index.md index 5a1d5d78..3d4b9d18 100644 --- a/blog/content/second-edition/posts/10-advanced-paging/index.md +++ b/blog/content/second-edition/posts/10-advanced-paging/index.md @@ -72,7 +72,7 @@ So in order to access page table frames, we need to map some virtual pages to th - While both of the above approaches work, there is a third technique called **recursive page tables** that combines their advantages: It keeps all page table frames mapped at all times so that no temporary mappings are needed, and also keeps the mapped pages together to avoid fragmentation of the virtual address space. This is the technique that we will use for our implementation, therefore it is described in detail in the following section. -## Recursive Page Tables +### Recursive Page Tables The idea behind this approach sounds simple: _Map some entry of the level 4 page table to the frame of level 4 table itself_. By doing this, we effectively reserve a part of the virtual address space and map all current and future page table frames to that space. Thus, the single entry makes every table of every level accessible through a calculatable address. @@ -102,7 +102,7 @@ Accessing the tables of levels 3 and 4 works in the same way. For accessing the It might take some time to wrap your head around the concept, but it works quite well in practice. -### Address Calculation +#### Address Calculation We saw that we can access tables of all levels by following the recursive entry once or multiple times before the actual translation. Since the indexes into the tables of the four levels are derived directly from the virtual address, we need to construct special virtual addresses for this technique. Remember, the page table indexes are derived from the address in the following way: From bcc590e65f25a26d512579289e5ad7b3d2385439 Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Fri, 25 Jan 2019 19:21:45 +0100 Subject: [PATCH 16/29] Create memory module in memory.rs instead of memory/mod.rs --- .../posts/10-advanced-paging/index.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/blog/content/second-edition/posts/10-advanced-paging/index.md b/blog/content/second-edition/posts/10-advanced-paging/index.md index 3d4b9d18..5f86e003 100644 --- a/blog/content/second-edition/posts/10-advanced-paging/index.md +++ b/blog/content/second-edition/posts/10-advanced-paging/index.md @@ -172,7 +172,7 @@ pub mod memory; ``` ```rust -// in src/memory/mod.rs +// in src/memory.rs use x86_64::PhysAddr; use x86_64::structures::paging::PageTable; @@ -277,7 +277,7 @@ The `x86_64` provides a [`RecursivePageTable`] type that implements safe abstrac [`RecursivePageTable`]: https://docs.rs/x86_64/0.3.5/x86_64/structures/paging/struct.RecursivePageTable.html ```rust -// in src/memory/mod.rs +// in src/memory.rs use x86_64::{VirtAddr, PhysAddr}; use x86_64::structures::paging::{Mapper, Page, PageTable, RecursivePageTable}; @@ -347,7 +347,7 @@ Let's start with the simple case and assume that we don't need to create new pag We implement it in a new `create_mapping` function in our `memory` module: ```rust -// in src/memory/mod.rs +// in src/memory.rs use x86_64::structures::paging::{FrameAllocator, PhysFrame, Size4KiB}; @@ -393,7 +393,7 @@ The [`map_to`] function can fail, so it returns a [`Result`]. Since this is just TODO ```rust -// in src/memory/mod.rs +// in src/memory.rs /// A FrameAllocator that always returns `None`. pub struct EmptyFrameAllocator; @@ -445,7 +445,7 @@ The white block in the middle of the screen is by our write to `0x1c00`, which m This only worked because there was already a level 1 table for mapping page `0x1000`. If we try to map a page for that no level 1 table exists yet, the `map_to` function tries to allocate frames from the `EmptyFrameAllocator` to create new page tables, which fails. We can see that happen when we try to map for example page `0xdeadbeaf000` instead of `0x1000`: ```rust -// in src/memory/mod.rs +// in src/memory.rs TODO: update create_example_mapping @@ -528,7 +528,7 @@ Note that we now pass `boot_info.p4_table_addr` instead of a hardcoded address t Now that we have access to the memory map through the boot information we can create a proper frame allocator on top. We start with a generic skeleton: ```rust -// in src/memory/mod.rs +// in src/memory.rs pub struct BootInfoFrameAllocator where I: Iterator { frames: I, @@ -551,7 +551,7 @@ The `frames` field can be initialized with an arbitrary [`Iterator`] of frames. The initialization of the `BootInfoFrameAllocator` happens in a new `init_frame_allocator` function: ```rust -// in src/memory/mod.rs +// in src/memory.rs use bootloader::bootinfo::{MemoryMap, MemoryRegionType}; From a3e7ad1fa8f1103140a779f619114780c825f206 Mon Sep 17 00:00:00 2001 From: Philipp Oppermann Date: Fri, 25 Jan 2019 19:56:54 +0100 Subject: [PATCH 17/29] Fix typo in graphics and replace SVGs with PNGs The SVG have rendering problems on some devices, e.g. when the text is zoomed. --- .../posts/10-advanced-paging/index.md | 12 ++++++------ .../recursive-page-table-access-level-1.png | Bin 0 -> 52566 bytes .../recursive-page-table-access-level-1.svg | 2 -- .../recursive-page-table-access-level-2.png | Bin 0 -> 51800 bytes .../recursive-page-table-access-level-2.svg | 2 -- .../recursive-page-table-access-level-3.png | Bin 0 -> 53659 bytes .../recursive-page-table-access-level-3.svg | 2 -- .../10-advanced-paging/recursive-page-table.png | Bin 0 -> 46989 bytes .../10-advanced-paging/recursive-page-table.svg | 2 -- .../temporarily-mapped-page-tables.png | Bin 0 -> 44984 bytes .../temporarily-mapped-page-tables.svg | 2 -- 11 files changed, 6 insertions(+), 16 deletions(-) create mode 100644 blog/content/second-edition/posts/10-advanced-paging/recursive-page-table-access-level-1.png delete mode 100644 blog/content/second-edition/posts/10-advanced-paging/recursive-page-table-access-level-1.svg create mode 100644 blog/content/second-edition/posts/10-advanced-paging/recursive-page-table-access-level-2.png delete mode 100644 blog/content/second-edition/posts/10-advanced-paging/recursive-page-table-access-level-2.svg create mode 100644 blog/content/second-edition/posts/10-advanced-paging/recursive-page-table-access-level-3.png delete mode 100644 blog/content/second-edition/posts/10-advanced-paging/recursive-page-table-access-level-3.svg create mode 100644 blog/content/second-edition/posts/10-advanced-paging/recursive-page-table.png delete mode 100644 blog/content/second-edition/posts/10-advanced-paging/recursive-page-table.svg create mode 100644 blog/content/second-edition/posts/10-advanced-paging/temporarily-mapped-page-tables.png delete mode 100644 blog/content/second-edition/posts/10-advanced-paging/temporarily-mapped-page-tables.svg diff --git a/blog/content/second-edition/posts/10-advanced-paging/index.md b/blog/content/second-edition/posts/10-advanced-paging/index.md index 5f86e003..16cd8d85 100644 --- a/blog/content/second-edition/posts/10-advanced-paging/index.md +++ b/blog/content/second-edition/posts/10-advanced-paging/index.md @@ -55,7 +55,7 @@ So in order to access page table frames, we need to map some virtual pages to th - Alternatively, we could **map the page tables frames only temporarily** when we need to access them. To be able to create the temporary mappings we only need a single identity-mapped level 1 table: - ![A virtual and a physical address space with an identity mapped level 1 table, which maps its 0th entry to the level 2 table frame, therey mapping that frame to page with address 0](temporarily-mapped-page-tables.svg) + ![A virtual and a physical address space with an identity mapped level 1 table, which maps its 0th entry to the level 2 table frame, therey mapping that frame to page with address 0](temporarily-mapped-page-tables.png) The level 1 table in this graphic controls the first 2 MiB of the virtual address space. This is because it is reachable by starting at the CR3 register and following the 0th entry in the level 4, level 3, and level 2 page tables. The entry with index `8` maps the virtual page at address `32 KiB` to the physical frame at address `32 KiB`, thereby identity mapping the level 1 table itself. The graphic shows this identity-mapping by the horizontal arrow at `32 KiB`. @@ -78,7 +78,7 @@ The idea behind this approach sounds simple: _Map some entry of the level 4 page Let's go through an example to understand how this all works: -![An example 4-level page hierarchy with each page table shown in physical memory. Entry 511 of the level 4 page is mapped to frame 4KiB, the frame of the level 4 table itself.](recursive-page-table.svg) +![An example 4-level page hierarchy with each page table shown in physical memory. Entry 511 of the level 4 page is mapped to frame 4KiB, the frame of the level 4 table itself.](recursive-page-table.png) The only difference to the [example at the beginning of this post] is the additional entry at index `511` in the level 4 table, which is mapped to physical frame `4 KiB`, the frame of the level 4 table itself. @@ -88,17 +88,17 @@ By letting the CPU follow this entry on a translation, it doesn't reach a level By following the recursive entry one or multiple times before we start the actual translation, we can effectively shorten the number of levels that the CPU traverses. For example, if we follow the recursive entry once and then proceed to the level 3 table, the CPU thinks that the level 3 table is a level 2 table. Going further, it treats the level 2 table as a level 1 table, and the level 1 table as the mapped frame. This means that we can now read and write the level 1 page table because the CPU thinks that it is the mapped frame. The graphic below illustrates the 5 translation steps: -![The above example 4-level page hierarchy with 5 arrows: "Step 0" from CR4 to level 4 table, "Step 1" from level 4 table to level 4 table, "Step 2" from level 4 table to level 3 table, "Step 3" from level 3 table to level 2 table, and "Step 4" from level 2 table to level 1 table.](recursive-page-table-access-level-1.svg) +![The above example 4-level page hierarchy with 5 arrows: "Step 0" from CR4 to level 4 table, "Step 1" from level 4 table to level 4 table, "Step 2" from level 4 table to level 3 table, "Step 3" from level 3 table to level 2 table, and "Step 4" from level 2 table to level 1 table.](recursive-page-table-access-level-1.png) Similarly, we can follow the recursive entry twice before starting the translation to reduce the number of traversed levels to two: -![The same 4-level page hierarchy with the following 4 arrows: "Step 0" from CR4 to level 4 table, "Steps 1&2" from level 4 table to level 4 table, "Step 3" from level 4 table to level 3 table, and "Step 4" from level 3 table to level 2 table.](recursive-page-table-access-level-2.svg) +![The same 4-level page hierarchy with the following 4 arrows: "Step 0" from CR4 to level 4 table, "Steps 1&2" from level 4 table to level 4 table, "Step 3" from level 4 table to level 3 table, and "Step 4" from level 3 table to level 2 table.](recursive-page-table-access-level-2.png) Let's go through it step by step: First the CPU follows the recursive entry on the level 4 table and thinks that it reaches a level 3 table. Then it follows the recursive entry again and thinks that it reaches a level 2 table. But in reality, it is still on the level 4 table. When the CPU now follows a different entry, it lands on a level 3 table, but thinks it is already on a level 1 table. So while the next entry points at a level 2 table, the CPU thinks that it points to the mapped frame, which allows us to read and write the level 2 table. Accessing the tables of levels 3 and 4 works in the same way. For accessing the level 3 table, we follow the recursive entry entry three times, tricking the CPU into thinking it is already on a level 1 table. Then we follow another entry and reach a level 3 table, which the CPU treats as a mapped frame. For accessing the level 4 table itself, we just follow the recursive entry four times until the CPU treats the level 4 table itself as mapped frame (in blue in the graphic below). -![The same 4-level page hierarchy with the following 3 arrows: "Step 0" from CR4 to level 4 table, "Steps 1,2,3" from level 4 table to level 4 table, and "Step 4" from level 4 table to level 3 table. In blue the alternative "Steps 1,2,3,4" arrow from level 4 table to level 4 table.](recursive-page-table-access-level-3.svg) +![The same 4-level page hierarchy with the following 3 arrows: "Step 0" from CR4 to level 4 table, "Steps 1,2,3" from level 4 table to level 4 table, and "Step 4" from level 4 table to level 3 table. In blue the alternative "Steps 1,2,3,4" arrow from level 4 table to level 4 table.](recursive-page-table-access-level-3.png) It might take some time to wrap your head around the concept, but it works quite well in practice. @@ -635,4 +635,4 @@ We're now able to map arbitrary pages and to allocate new physical frames when w TODO spellcheck TODO improve transition between sections TODO update post date -TODO check level 2 table diagram 24KiB -> 32KiB \ No newline at end of file +TODO use PNGs instead of SVGs? diff --git a/blog/content/second-edition/posts/10-advanced-paging/recursive-page-table-access-level-1.png b/blog/content/second-edition/posts/10-advanced-paging/recursive-page-table-access-level-1.png new file mode 100644 index 0000000000000000000000000000000000000000..1c6662ab32b22581afa4af5848ecd290b6eca93f GIT binary patch literal 52566 zcmeAS@N?(olHy`uVBq!ia0y~yU~*w#U=rY9V_;xN_+Pl2fq~DyDkP#Lx5B+Bu^_`Y zKP5GXfx$H5INuwq{JL4pD&5r&-|X;r##Pt3>Gc8s_?r|2eEu^Z{I9TsJGef8ZSg_Yga29uG?-Ej#P`1bHvPNJ z`TEVOcK_EN-@jzXnfCvSB_9Wu$Npg#{8+E(@N2z5+y4bR6`v;6-uSlve3k7R@g4CZ zAMIJbmFHL<=wgZZxc^}Hl;yfVc5obNI>687oV54JQI51u{mb`T`)eX!7yj67!t&mo>ig?Qpt2WDA|72xz$D+=8aqj0cO%{2Nem@b4(&1gEv{OAv%2irY zscz!dxL}^O0$&^_pSp2^dB#lM{ZTu2ukwj8ZZval)6|&KaPDi=2 z9Wuh?S2T(Va;@xGwYN(CxaIrGowu&$l%;CzFgxIkwi{H%eRR*)4-N=h^UEUHh^QLTKtKZsY-t1c6%?4*<)Bap3 zyjRC|B}4C=L;pL&`G(W$?PGQ=Ycrp51#^P2kvoPNM#$Dg{n&k@{*W@Vt zU-y0TA@dvIr!BQu6_X_+>vz6O^L{afUm?!zmi7;&csu<`757W#bjIq**Snib$!~sQ zuq5Q*tBD&H%WUYB;LmvA`o6sPPsCyty_OR#k}KEtg#K{z6FmB7ZT-clWw(B>>)W_) zZpyvm$)9H!g?62_4SDqVaPIo~@l&UToqHE{Qf>Z~PcL^WeDl>g$I{V%N}%W{cXiy$ z=OSSSmp~`|7m+j^h0sy1Om;5AEd3*i_;5=-vhglknZLY{DNaj#p&F zOj7ZdOKLD)eCYKCkJq#Q%5-QyY?zr8lx25r6~|WFEv(P1N@pyrpK+$V%2#}`?5)+G zXWrQx8=>30cVpb`iC;IoDbH337MozvVUX#%ru&Rl}Wrt z_wTo<$?o1e_ivLgzG!>lMxJF?=Z5MniaEb_96tMGn+-#2EB7(yV9WH(<2pt=n=jbC zk~+Pw*_w6MrjXESwjLP^R!vH%YFcw$cy3C;;gB=SuIn`NF!JY2*EYGQQrtz@N@6i-sS+6r~^lNU9t|W(%lhm^T$E{^4=>h>F%}{&z-Zn8NDXujI!L3 zJkc22(=V*+%~TWqM$M90DB!m|yH>f4fDoAFMHWv^iS0O|@}m+0xoa-+Jc#-Mua1%9rWy;@oTRZThis?|jynH;d=^ zUiaoXzu?pM?oFT1m}@Mrz4FbK*TcWsz^ZFc?u@VRPwwtr$+SH%mm~h={KtRa%wNC} zkv?DHK<-kn$fZg1Ep2)Y-buL`_`N*6Wmb@j)-OY$mYeDm5+ml7@+NE7_qgm@6ZKpA zyGjZF{cF?sQtwJ^Q+hZ3K$*br)Rf=aS30gFsy%)ra5o~rtNGUvw@II`IbMrDaQax1 zjqT28l``Q9-R)=9f2gkix#ikdqqsX+FM5(!GdH#J2NWHdclhHaTjfS(Ri>v;7tP2i z`zfX(vcYdf-d{V#xn{NdmY9~#ir;cO-KWFvQl3}hgi49}7OofmyhGuq zfrsV%Bk^;W%<Y|0+6=S!t*;=D;&pJeSL9-Y3+xg)J!Oyl07OJX;~RP5raFPsZs zGvflEb$-IB3)MB9kK&d(RsNr_Us8QiMrPqp)5)_HZwjnPyYMvXE6eBCMjnT^9eelW zrcJv}+P==9_m`D)(#v0RR;gGY-Wb(yHa*0AqtdbVd{$qxH;0wx{49R4zjf-D+7m*H z3v}i?J-qPe?xN0fk89mO9iCUKxN?c4U2K=){j&mxeV^D(h~1;QcEZ!ziF=~v`+xu3 z`q^UP5?%|AcgN2(%3Qyg9ec}FWliL|_?YHM!MDNOrd!i264&3G^-{5Y@e+1kqq)&a z`&R1o@fN+PPxpHBl!I%{v3}bgF3*%|(KB!3mP@_lymhM1+*kcbLSX+VtAl;7Hr4I0 z3uW4KXc@cD!J|tTgn8U`vfH%0>y_P}c6*0AQ>SFy@$=hSA{w)Edb`CW+2rLP0^H|? zZc6Ge-1SxJXo79-Ov_c+y(WzcV+xX-@d=BF+=A3!YvNQp)tmJnyF>RXMM%P z6mpJS*i#X@_{98~UaBW}=1O{Vg&EGtGv0i#lV_>X^16$+%U90uO3+>QtIx#JZC3vQ z1-|*qazg)>9;`H-={ zYKlpxgK62y_i~kHLiR_**G|lw!Sbq^=l+Jx@2YwV=aU_E_Uiu2%9g^hkp(7O zHakDjo#@)Mg~P&}L1vCO*QxJ)oa~F$626(0eKnB&zNo9sSg-HB@$sWS=kC?Z`aRpV zifQYuwy%<(twnp+3tr0IZ{8sHe9=bT>ig|UM-vYoO#1M$>q+v#(qeYz$m|b07e9>r zvEsti@{Y_^JETwTd#tngN%Q)&Nf8$Q%#K020hj)+t@2NEOTHw*KJ#5mUe_n z9_!04cSzfz7PI@9;>#=93J&Fh)2>?m`Pp25LeXNw*Qp`#LK99|=NhH*{8%o1!D(8c z{j~7+7dW{Jcl|v1xJdn;$>m23#@^j*-rNmG<$T|-S~E{BC?~Otr*_e_f6}~V`*JUC z%?~}?^?gGzv-UfaC5Kaez8yMK^hZKDZ*%;KZ8vL5zEyGyzWQ=@hRVEe6BuMUUK>CC zcxe8_mpiuZ+bq87%+tT38v`oknl6PubKg|-W#&DDP?-r_H`hck*KD?#yzTYd=&kK; zQ*OA}8UE1ro)f(N*PYt*XACVmyFx4^r%$_>qS;?y7XGka!^Wf0Ag-MDl zSl48&k>@`3w7I5O`t`FtsVepp16TAttZVt&8ZkRqV%f!>xVh7=r@r14)Uv7Qo!^Bw z3;CIO8&7#my4mU-QNCK@Q|P=f30{p^W&O*YvsMOOzU<D?|h_d1)qKV@%!>+tNcuZ(Te26HVHMXlu*{d0?KZr`5$+xC`-+O4g&`z~}W z_R4z0bBE=}!_~jIqZAE|@?BJ7)pO=dZdNi+C_j8~%Q6K9A<=94w;l>1#~&IFtHN-H&9 zl%19;j9;do{QcAU=%;;GXHH(w($uSAw*TqFw+ky?I$E?vkXS`5RBKnb_wN)x`I{#Oks^rIu?@XPL+u ziRrhkpG~WbnQ8cx^Vnap>ezL5+YOV-f zcmA!~>g}&T%w9iJ@aHi}$MR=hJqN!@-@QCDs6WU)o-ZtO9 zdgG~x*RG{GPwcjK2r}JS_$nuFk}txSi{5M(ugfns zIQE+R;=b>4#ZT&`{`AH2`c?(^=6YWHvT=!yi)FQTv;4X_dcnW^Ba}A(V)|@q_afm# z@TuSjZ+b0aDi==gkN!UI+WFfHe{avbdarT&-}Yo}Zue^4_meERcQR*Y&WXA;J4P^F z@xXJomEWhXymnmYWXqC2Z=+6{YjOtW<-R&Rhx5JlRzxx| zC@^@sIEGZrc{8`XLgebdcKaC&O0pZ9MLJDbRXCJZH2m$d-`n)URX@UjYsCvzmkkZF z+Hrft*4ZjFc5`((1vu{Z@crA32Eo& zSf+2AW4@fJNr8hfTF`usA%~%h@eS*TR?f-_z5{#=H?1D?vpX=<{yFkdXF9KgSc5J@ z9Gie_RG9V=vlT{GOpH%5`}`SRJbPYcdtUQKx+d6`w!;j^W>ox7yb#_Q&obTT%SFNa zn`2@b{;)onx}YeXXSV78{x+?{&9jP)AH;Vs)SmZzzgdLEQGn%O^C~5mVg{SO3#}Xs zLX0^)O8IVvo}cUUoxT_}cr!0ibW#DCpQtiH;40e(#fA_D?*&U1$u?LqTyqS4_nP6$ zrsMOOAE-1`GOjCMuw3Xpe}Y*<+KL$hx{MPz9|$t6X8gmKpxa>n;NH}090$HLe0uxQ zoxy_P>esJR&K3PUG+V&YeV)wuOpXSV>U(KSE1s+NH3xjw0NHr8&%wz=bd}QDOnW&t z1#yR1hOG=TjafSjFK`^-ntR>4Z}Zy{)D!vE^F8*3fPH zsIN^(h{1y2L9>C~WWD*8`_~m+s!l!Sj(2*Z@83}6ca-7W#W~V^4|p2bW?9^1dlD$X z;wZ36_Fu~i^^m7?IaS5_Hb@_^sGcMD&0_lP{^^Vs<{hv9at7)&gfg7lBp<%zw9o8! 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