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Fix typos in 06 and 07 posts. (#487)

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Donald Pinckney
2018-10-25 08:27:37 -04:00
committed by Philipp Oppermann
parent 7df441c014
commit 1ed19359b5
2 changed files with 2 additions and 2 deletions
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2
blog/content/second-edition/posts/06-cpu-exceptions/index.md
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@@ -221,7 +221,7 @@ pub fn init_idt() {
} }
``` ```
Now we can add handler functions. We start by adding a handler for the [breakpoint exception]. The breakpoint exception is the perfect exception to test exception handling. Its only purpose is to temporary pause a program when the breakpoint instruction `int3` is executed. Now we can add handler functions. We start by adding a handler for the [breakpoint exception]. The breakpoint exception is the perfect exception to test exception handling. Its only purpose is to temporarily pause a program when the breakpoint instruction `int3` is executed.
[breakpoint exception]: http://wiki.osdev.org/Exceptions#Breakpoint [breakpoint exception]: http://wiki.osdev.org/Exceptions#Breakpoint

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blog/content/second-edition/posts/07-double-faults/index.md
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@@ -329,7 +329,7 @@ The problem is that the GDT segments are not yet active becaues the segment and
In summary, we need to do the following: In summary, we need to do the following:
1. **Reload code segment register**: We changed our GDT, so we should reload `cs`, the code segment register. This required since the old segment selector could point a different GDT descriptor now (e.g. a TSS descriptor). 1. **Reload code segment register**: We changed our GDT, so we should reload `cs`, the code segment register. This is required since the old segment selector could point a different GDT descriptor now (e.g. a TSS descriptor).
2. **Load the TSS** : We loaded a GDT that contains a TSS selector, but we still need to tell the CPU that it should use that TSS. 2. **Load the TSS** : We loaded a GDT that contains a TSS selector, but we still need to tell the CPU that it should use that TSS.
3. **Update the IDT entry**: As soon as our TSS is loaded, the CPU has access to a valid interrupt stack table (IST). Then we can tell the CPU that it should use our new double fault stack by modifying our double fault IDT entry. 3. **Update the IDT entry**: As soon as our TSS is loaded, the CPU has access to a valid interrupt stack table (IST). Then we can tell the CPU that it should use our new double fault stack by modifying our double fault IDT entry.